參數(shù)資料
型號(hào)： IDT82V2048DAG
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 6/62頁(yè)
文件大?。?/td> 0K
描述： IC LIU T1/E1 8CH SHORT 144-TQFP
標(biāo)準(zhǔn)包裝： 30
類(lèi)型： 線(xiàn)路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.13 V ~ 3.47 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-TQFP（20x20）
包裝： 托盤(pán)
其它名稱(chēng)： 82V2048DAG
14
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
2.3
CLOCK EDGES
The active edge of RCLKn and SCLK are selectable. If pin CLKE is
high, the active edge of RCLKn is the rising edge, as for SCLK, that is
falling edge. On the contrary, if CLKE is low, the active edge of RCLK is
the falling edge and that of SCLK is rising edge. Pins RDn/RDPn, CVn/
RDNn and SDO are always active high, and those output signals are
clocked out on the active edge of RCLKn and SCLK respectively. See
However, in dual rail mode without clock recovery, pin CLKE is used to
set the active level for RDPn/RDNn raw slicing output: High for active
high polarity and low for active low. It should be noted that data on pin
SDI are always active high and are sampled on the rising edges of
SCLK. The data on pin TDn/TDPn or BPVIn/TDNn are also always
active high but are sampled on the falling edges of TCLKn, despite the
level on CLKE.
2.4
RECEIVER
In receive path, the line signals couple into RRINGn and RTIPn via a
transformer and are converted into RZ digital pulses by a data slicer.
Adaptation for attenuation is achieved using an integral peak detector
that sets the slicing levels. Clock and data are recovered from the
received RZ digital pulses by a digital phase-locked loop that provides
jitter accommodation. After passing through the selectable jitter attenu-
ator, the recovered data are decoded using B8ZS/HDB3 or AMI line
code rules and clocked out of pin RDn in single rail mode, or presented
on RDPn/RDNn in an undecoded dual rail NRZ format. Loss of signal,
alarm indication signal, line code violation and excessive zeros are
detected. The presence of programmable inband loopback codes are
also detected. These various changes in status may be enabled to
generate interrupts.
2.4.1
PEAK DETECTOR AND SLICER
The slicer determines the presence and polarity of the received
pulses. In data recovery mode, the raw positive slicer output appears on
RDPn while the negative slicer output appears on RDNn. In clock and
data recovery mode, the slicer output is sent to Clock and Data
Recovery circuit for abstracting retimed data and optional decoding. The
slicer circuit has a built-in peak detector from which the slicing threshold
is derived. The slicing threshold is default to 50% (typical) of the peak
value.
Signals with an attenuation of up to 12 dB (from 2.4 V) can be recov-
ered by the receiver. To provide immunity from impulsive noise, the peak
detectors are held above a minimum level of 0.150 V typically, despite
the received signal level.
2.4.2
CLOCK AND DATA RECOVERY
The Clock and Data Recovery is accomplished by Digital Phase
Locked Loop (DPLL). The DPLL is clocked 16 times of the received
clock rate, i.e. 24.704 MHz in T1 mode or 32.768 MHz in E1 mode. The
recovered data and clock from DPLL is then sent to the selectable Jitter
Attenuator or decoder for further processing.
The clock recovery and data recovery mode can be selected on a per
channel basis by setting bit CRSn in register e-CRS. When bit CRSn is
defaulted to ‘0’, the corresponding channel operates in data and clock
recovery mode. The recovered clock is output on pin RCLKn and re-
timed NRZ data are output on pin RDPn/RDNn in dual rail mode or on
RDn in single rail mode. When bit CRSn is set to ‘1’, dual rail mode with
data recovery is enabled in the corresponding channel and the clock
recovery is bypassed. In this condition, the analog line signals are
converted to RZ digital bit streams on the RDPn/RDNn pins and inter-
nally connected to an EXOR which is fed to the RCLKn output for
external clock recovery applications.
If MCLK is pulled high, all the receivers will enter the dual rail mode
with data recovery. In this case, register e-CRS is ignored.
Table-3 System Interface Configuration (In Host Mode)
Pin MCLK
Pin TDNn
CRSn in e-CRS
SINGn in e-SING
Interface
Clocked
High
0
Single Rail Mode 1
Clocked
Pulse
0
1
Single Rail Mode 2
Clocked
Pulse
0
Dual Rail mode with Clock Recovery
Clocked
Pulse
1
0
Dual Rail mode with Data Recovery. Receive just slices the incoming data. Transmit is
determined by the status of TCLKn.
High
Pulse
-
Dual Rail mode with Data Recovery. Receive just slices the incoming data. Transmit is
determined by the status of TCLKn.
Low
Pulse
-
Receiver is powered down. Transmit is determined by the status of TCLKn.
Table-4 Active Clock Edge and Active Level
Pin CLKE
Pin RDn/RDPn and CVn/RDNn
Pin SDO
Clock Recovery
Slicer Output
High
RCLKn
Active High
SCLK
Active High
Low
RCLKn
Active High
Active Low
SCLK
Active High
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參數(shù)描述
IDT82V2048E 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:OCTAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
IDT82V2048EBB 功能描述:IC LIU T1/E1 8CH SHORT 208-BGA RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
IDT82V2048EBBG 功能描述:IC LINE INTERFACE UNIT 208-PBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類(lèi)型:驅(qū)動(dòng)器 驅(qū)動(dòng)器/接收器數(shù):4/0 規(guī)程:RS422 電源電壓:4.5 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC N 包裝:帶卷 (TR)
IDT82V2048EDR 功能描述:IC LIU T1/E1 8CH SHORT 208-TQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
IDT82V2048L 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
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