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參數(shù)資料
| 型號(hào)： | IDT82P2288BB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Octal T1/E1/J1 Long Haul Short Haul Transceiver |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PBGA256 |
| 封裝： | PLASTIC, BGA-256 |
| 文件頁數(shù)： | 28/375頁 |
| 文件大小： | 2430K |
| 代理商： | IDT82P2288BB |
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IDT82P2281
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
17
October 7, 2003
3.7
DECODER
3.7.1
LINE CODE RULE
3.7.1.1
T1 / J1 Mode
In T1/J1 mode, the AMI and B8ZS line code rules are provided. The
selection is made by the R_MD bit.
3.7.1.2
E1 Mode
In E1 mode, the AMI and HDB3 line code rules are provided. The
selection is made by the R_MD bit.
3.7.2
DECODE ERROR DETECTION
3.7.2.1
T1 / J1 Mode
The decode errors can be divided into three types in T1/J1 mode:
1. Bipolar Violation (BPV) Error: When AMI line code rule is used,
the BPV error will be detected if two consecutive pulses are received
with the same polarity (refer to Figure 6). The event of the Bipolar Viola-
tion (BPV) Error is forwarded to the Performance Monitor.
2. B8ZS Code Violation (CV) Error: When B8ZS line code rule is
used, a CV error is detected when the received code does not match the
standard B8ZS line code pattern (expect the Excessive Zero error).
3. Excessive Zero (EXZ) Error: EXZ error can be detected in both
AMI and B8ZS line code rules. There are two standards defining the
EXZ error: ANSI and FCC. The EXZ_DEF bit chooses a standard for the
corresponding link to judge the EXZ error. Table 8 shows the definition of
EXZ. To count the event of the Excessive Zero (EXZ) Error, the
EXZ_ERR[1:0] bits should be set to ‘01’. The Excessive Zero (EXZ)
Error is counted in an internal 16-bit EXZ counter. The content in the
EXZ counter is transferred to the EXZ Error Counter L-Byte & H-Byte
registers in two ways:
a. When the CNT_MD bit is ‘0’, the Manual-Report mode is
selected. The EXZ counter transfers its content to the EXZ Error
Counter L-Byte & H-Byte registers when there is a transition from ‘0’ to
‘1’ on the CNT_TRF bit;
b. When the CNT_MD bit is ‘1’, the Auto-Report mode is selected.
The EXZ counter transfers its content to the EXZ Error Counter L-Byte &
H-Byte registers every one second automatically.
After the content in the counter is transferred to the EXZ Error
Counter L-Byte & H-Byte registers, the counter will be cleared to ‘0’ and
start a new round counting automatically. No error event is lost during
data transferring.
The overflow of the counter is reflected by the CNTOV_IS bit, and
can trigger an interrupt if the corresponding CNT_IE bit is set.
When the Bipolar Violation (BPV) Error or the B8ZS Code Violation
(CV) Error is detected, it will be indicated by the CV_IS bit. When the
Excessive Zero (EXZ) Error is detected, it will be indicated by the
EXZ_IS bit. When the CV_IS bit or the EXZ_IS bit is ‘1’, an interrupt will
be reported by the
INT
pin if enabled by the corresponding CV_IE bit or
the EXZ_IE bit.
3.7.2.2
E1 Mode
The decode errors can be divided into three types in E1 mode:
1. Bipolar Violation (BPV) Error: When AMI line code rule is used,
the BPV error will be detected if two consecutive pulses are received
with the same polarity (refer to Figure 6). The event of the Bipolar Viola-
tion (BPV) Error is forwarded to the Performance Monitor.
2. HDB3 Code Violation (CV) Error: When HDB3 line code rule is
used, a CV error is detected if two consecutive BPV errors are detected,
and the pulses that have the same polarity as the previous pulse are not
the HDB3 zero substitution pulsed (refer to Figure 8).
3. Excessive Zero (EXZ) Error: EXZ error can be detected in both
AMI and HDB3 line code rules. There are two standards defining the
EXZ error: ANSI and FCC. The EXZ_DEF bit chooses a standard for the
corresponding link to judge the EXZ error. Table 8 shows the definition of
EXZ. To count the event of the Excessive Zero (EXZ) Error, the
EXZ_ERR[1:0] bits should be set to ‘01’. The Excessive Zero (EXZ)
Error is counted in an internal 16-bit EXZ counter. The content in the
EXZ counter is transferred to the EXZ Error Counter L-Byte & H-Byte
registers in two ways:
a. When the CNT_MD bit is ‘0’, the Manual-Report mode is
selected. The EXZ counter transfers its content to the EXZ Error
Counter L-Byte & H-Byte registers when there is a transition from ‘0’ to
‘1’ on the CNT_TRF bit;
b. When the CNT_MD bit is ‘1’, the Auto-Report mode is selected.
The EXZ counter transfers its content to the EXZ Error Counter L-Byte &
H-Byte registers every one second automatically.
After the content in the counter is transferred to the EXZ Error
Counter L-Byte & H-Byte registers, the counter will be cleared to ‘0’ and
start a new round counting automatically. No error event is lost during
data transferring.
The overflow of the counter is reflected by the CNTOV_IS bit, and
can trigger an interrupt if the corresponding CNT_IE bit is set.
When the Bipolar Violation (BPV) Error or the HDB3 Code Violation
(CV) Error is detected, it will be indicated by the CV_IS bit. When the
Excessive Zero (EXZ) Error is detected, it will be indicated by the
EXZ_IS bit. When the CV_IS bit or the EXZ_IS bit is ‘1’, an interrupt will
be reported by the
INT
pin if enabled by the corresponding CV_IE bit or
the EXZ_IE bit.
Table 8: Excessive Zero Error Definition
ANSI
FCC
AMI
More than 15 consecutive 0s are
detected.
B8ZS
More than 7 consecutive 0s are
detected (refer to Figure 7).
HDB3
More than 3 consecutive 0s are
detected (refer to Figure 8).
More than 80 consecutive 0s are
detected.
More than 7 consecutive 0s are
detected (refer to Figure 7).
More than 3 consecutive 0s are
detected (refer to Figure 8).
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| IDT82P2288BB8 | 功能描述:TXRX T1/J1/E1 8CHAN 256-PBGA RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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