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參數(shù)資料
| 型號(hào)： | IDT82P2288BB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Octal T1/E1/J1 Long Haul Short Haul Transceiver |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PBGA256 |
| 封裝： | PLASTIC, BGA-256 |
| 文件頁數(shù)： | 21/375頁 |
| 文件大?。?/td> | 2430K |
| 代理商： | IDT82P2288BB |
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IDT82P2281
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
10
October 7, 2003
3
FUNCTIONAL DESCRIPTION
The IDT82P2281 is a highly featured single device solution for T1/
E1/J1 trunks. The configuration is performed through an SPI or parallel
microprocessor interface.
LINE INTERFACE - RECEIVE PATH
In the receive path, the signals from the line side are coupled into
the RTIP and RRING pins and pass through an Impedance Terminator.
An Adaptive Equalizer is provided to increase the sensitivity for small
signals. Clock and data are recovered from the digital pulses output from
the slicer. After passing through the Receive Jitter Attenuator (can be
enabled or disabled), the recovered data is decoded using B8ZS (for T1/
J1) / HDB3 (for E1) or AMI line code rules and clocked into the Frame
Processor. Loss of signal, line code violations and excessive zero are
detected.
FRAMER - RECEIVE PATH
In T1/J1 Mode, the recovered data and clock can be configured in
Super Frame (SF), Extended Super Frame (ESF), T1 Digital Multiplexer
(DM) or Switch Line Carrier - 96 (SLC-96) formats. (The T1 DM and
SLC-96 formats only exist in T1 mode). The framing can also be
bypassed (unframed mode). The Framer detects and indicates the out
of SF/ESF/DM/SLC-96 synchronization event, the Yellow, Red and AIS
alarms. The Framer also detects the presence of inband loopback codes
and bit-oriented messages. Frame Alignment Signal errors, CRC-6
errors, out of SF/ESF/T1 DM/SLC-96 events and Frame Alignment posi-
tion changes are counted. Up to three HDLC links (in ESF and T1 DM
format) or two HDLC links (in SF and SLC-96 format) are provided to
extract the HDLC message on the DL bit (in ESF format) / D bit in CH24
(in T1 DM format) or any arbitrary position. In the T1/J1 receive path,
signaling debounce, signaling freeze, idle code substitution, digital milli-
watt code insertion, idle code insertion, data inversion and pattern gen-
eration or detection are supported on a per-channel basis. An Elastic
Store Buffer that supports controlled slip and adaptation to backplane
timing may be enabled. In the Receive System Interface, various operat-
ing modes can be selected to output signals to the system.
In E1 Mode, the recovered data and clock can be configured to
frame to Basic Frame, CRC Multi-Frame and Signaling Multi-Frame.
The framing can be bypassed (unframed mode). The Framer detects
and indicates the following event: out of Basic Frame Sync, out of CRC
Multi-Frame, out of Signaling Multi-Frame, Remote Alarm Indication sig-
nal and Remote Signaling Multi-Frame Alarm Indication signal. The
Framer also monitors Red and AIS alarms. Basic Frame Alignment Sig-
nal errors, Far End Block Errors (FEBE) and CRC errors are counted.
Up to three HDLC links are provided to extract the HDLC message on
TS16, the Sa National bits or any arbitrary timeslot. In the E1 receive
path, signaling debounce, signaling freezing, idle code substitution, digi-
tal milliwatt code insertion, trunk conditioning, data inversion and pattern
generation or detection are also supported on a per-timeslot basis. An
Elastic Store Buffer that supports slip buffering and adaptation to back-
plane timing may be enabled. In the Receive System Interface, various
operating modes can be selected to output signals to the system.
SYSTEM INTERFACE
On the system side, if the device is in T1/J1 mode, the data stream
of 1.544 Mbit/s can be converted to/from the data stream of 2.048 Mbit/s
by software configuration. In addition, the link can be multiplexed to or
de-multiplexed from a 8.192 Mbit/s bus. If the device is in E1 mode, the
link can be multiplexed to or de-multiplexed from a 8.192 Mbit/s bus.
FRAMER - TRANSMIT PATH
In the transmit path, the Transmit System Interface inputs the sig-
nals with various operating modes. In T1/J1 mode, the signals can be
processed by a Transmit Payload Control to execute the signaling inser-
tion, idle code substitution, data insertion, data inversion and test pattern
generation or detection on a per-channel basis. The transmit path of
each transceiver can be configured to generate SF, ESF, T1 DM or SLC-
96. The framer can also be disabled (unframed mode). The Framer can
transmit Yellow alarm and AIS alarm. Inband loopback codes and bit ori-
ented message can be transmitted. Up to three HDLC links (in ESF and
T1 DM format) or two HDLC links (in SF and SLC-96 format) are pro-
vided to insert the HDLC message on the DL bit (in ESF format) / D bit in
CH24 (in T1 DM format) or any arbitrary position. After passing through
a Transmit Buffer, the processed data and clock are input to the
Encoder.
In E1 mode, the signals can be processed by a Transmit Payload
Control to execute the signaling insertion, idle code substitution, data
insertion, data inversion and test pattern generation or detection on a
per-timeslot basis. The transmit path of each transceiver can be config-
ured to generate Basic Frame, CRC Multi-Frame and Signaling Multi-
Frame. The framer can be disabled (unframed mode). The Framer can
transmit Remote Alarm Indication signal, the Remote Signaling Multi-
Frame Alarm Indication signal, AIS alarm and FEBE. Three HDLC links
are provided to insert the HDLC message on TS16, the Sa National bits
or any arbitrary timeslot. The processed data and clock are input to the
Encoder.
LINE INTERFACE - TRANSMIT PATH
The data is encoded using AMI or B8ZS (for T1/J1) and HDB3 (for
E1) line code rules. The Transmit Jitter Attenuator, if enabled, is pro-
vided with a FIFO in the transmit data path. A de-jittered clock is gener-
ated by an integrated digital phase-locked loop and is used to read data
from the FIFO. The shapes of the pulses are user programmable to
ensure that the T1/E1/J1 pulse template is met after the signal passing
through different cable lengths and types. Bipolar violation can be
inserted for diagnostic purposes if AMI line code rule is enabled. The
signal is transmitted on the TTIP and TRING pins through an Impedance
Terminator.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| IDT82P2288BB8 | 功能描述:TXRX T1/J1/E1 8CHAN 256-PBGA RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82P2288BBBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Octal T1/E1/J1 Long Haul / Short Haul Transceiver |
| IDT82P2288BBG | 功能描述:TXRX OCTAL T1/E1/J1 256-PBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82P2288BBG8 | 功能描述:TXRX T1/J1/E1 8CHAN 256-PBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82P2521 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:21(1) Channel High-Density E1 Line Interface Unit |
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