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| 型號(hào)： | IDT82P2282PFG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 359/381頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX T1/J1/E1 2CH 100TQFP |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 2/2 |
| 規(guī)程： | T1/E1/J1 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x20） |
| 包裝： | 托盤 |
| 其它名稱： | 82P2282PFG IDT82P2282PFG-ND |
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
79
August 20, 2009
3.18.2
E1 MODE
In E1 mode, the Transmit System Interface can be set in Non-multi-
plexed Mode or Multiplexed Mode. In the Non-multiplexed Mode, the
TSDn pin is used to input the data to each link at the bit rate of 2.048
Mb/s. While in the Multiplexed Mode, the data is byte interleaved from
one high speed data stream and inputs on the MTSD pin at the bit rate
of 8.192 Mb/s.
In the Non-multiplexed mode, if the TSCK is from outside, the
transmit system interface is in Transmit Clock Slave mode, otherwise if
the device outputs clock to TSCK itself, the transmit system interface is
in Transmit Clock Master mode.
In the Transmit Clock Master mode, if TSCKn outputs pulses during
the entire E1 frame, the Transmit System Interface is in Transmit Clock
Master Full E1 mode. If only the clocks aligned to the selected timeslots
are output on TSCKn, the Transmit System Interface is in Transmit
Clock Master Fractional E1 mode.
Table 43 summarizes how to set the transmit system interface of
each link into various operating modes and the pins’ direction of the
transmit system interface in different operating modes.
3.18.2.1
Transmit Clock Master Mode
In the Transmit Clock Master mode, each link uses its own timing
signal on the TSCKn pin and framing pulse on the TSFSn pin to input
the data on each TSDn pin. The signaling bits on the TSIGn pin are per-
timeslot aligned with the data on the TSDn pin.
In the Transmit Clock Master mode, the data on the system inter-
face is clocked by the TSCKn. The active edge of the TSCKn used to
update the pulse on the TSFSn is determined by the FE bit. The active
edge of the TSCKn used to sample the data on the TSDn and TSIGn is
determined by the DE bit. If the FE bit and the DE bit are not equal, the
pulse on the TSFSn is ahead.
In the Transmit Clock Master mode, the TSFSn can indicate the
Basic frame, CRC Multi-frame and/or Signaling Multi-frame. The indica-
tions are selected by the FSTYP bit. The active polarity of the TSFSn is
selected by the FSINV bit.
The Transmit Clock Master mode includes two sub-modes: Trans-
mit Clock Master Full E1 mode and Transmit Clock Master Fractional E1
mode.
3.18.2.1.1
Transmit Clock Master Full E1 Mode
Besides all the common functions described in the Transmit Clock
Master mode, the special feature in this mode is that the TSCKn is a
standard 2.048 MHz clock, and the data in all 32 timeslots in a standard
E1 frame are clocked in by the TSCKn.
3.18.2.1.2
Transmit Clock Master Fractional E1 Mode
Besides all the common functions described in the Transmit Clock
Master mode, the special feature in this mode is that the TSCKn is a
gapped 2.048 MHz clock (no clock signal during the selected timeslot).
The TSCKn is gapped during the timeslots or the Bit 8 duration by
selecting the G56K & GAP bits in the Transmit Payload Control. The
data in the corresponding gapped duration is a don't care condition.
3.18.2.2
Transmit Clock Slave Mode
In the Transmit Clock Slave mode, the timing signal on the TSCKn
pin and the framing pulse on the TSFSn pin to input the data on the
TSDn pin are provided by the system side. When the TSLVCK bit is set
to ‘0’, each link uses its own TSCKn and TSFSn; when the TSLVCK bit
is set to ‘1’ and both two links are in the Transmit Clock Slave mode, the
two links use the TSCK[1] and TSFS[1] to input the data. The signaling
bits on the TSIGn pin are per-timeslot aligned with the data on the TSDn
pin.
In the Transmit Clock Slave mode, the data on the system interface
is clocked by the TSCKn. The active edge of the TSCKn used to sample
the pulse on the TSFSn is determined by the FE bit. The active edge of
the TSCKn used to sample the data on the TSDn and TSIGn is deter-
mined by the DE bit. If the FE bit and the DE bit are not equal, the pulse
on the TSFSn is ahead. The speed of the TSCKn can be selected by the
CMS bit to be the same rate as the data rate on the system side (2.048
Mb/s) or double the data rate (4.096 Mb/s). If both two links use the
TSCK[1] and TSFS[1] to input the data, the CMS bit of the two links
should be set to the same value. If the speed of the TSCKn is double the
data rate, there will be two active edges in one bit duration. In this case,
the EDGE bit determines the active edge to sample the data on the
TSDn and TSIGn pins. The pulse on the TSFSn pin is always sampled
on its first active edge.
In the Transmit Clock Slave mode, the TSFSn can indicate the
Basic frame, CRC Multi-frame and/or Signaling Multi-frame. The indica-
tions are selected by the FSTYP bit. The active polarity of the TSFSn is
Table 43: Operating Modes Selection In E1 Transmit Path
TMUX
TMODE
G56K, GAP
Operating Mode
Transmit System Interface Pin
Input
Output
0
00
Transmit Clock Master Full E1
TSDn, TSIGn
TSCKn, TSFSn
not both 0s 1
Transmit Clock Master Fractional E1
1
X
Transmit Clock Slave
TSCKn, TSFSn, TSDn, TSIGn
X
1
X
Transmit Multiplexed
MTSCK, MTSFS, MTSD, MTSIG
X
NOTE:
1. When the G56K, GAP bits in TPLC indirect registers are set, the PCCE bit must be set to ‘1’.
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