參數(shù)資料
型號(hào)： IDT82P2282PF
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 344/381頁(yè)
文件大?。?/td> 0K
描述： TXRX T1/J1/E1 2CHAN 100-TQFP
標(biāo)準(zhǔn)包裝： 15
類(lèi)型： 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 2/2
規(guī)程： T1/E1/J1
電源電壓： 3 V ~ 3.6 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x20）
包裝： 托盤(pán)
其它名稱(chēng)： 82P2282PF
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
65
August 20, 2009
3.17
RECEIVE SYSTEM INTERFACE
The Receive System Interface determines how to output the
received data stream to the system backplane. The data from the two
links can be aligned with each other or be output independently. The tim-
ing clocks and framing pulses can be provided by the system backplane
or obtained from the far end. The Receive System Interface supports
various configurations to meet various requirements in different applica-
tions.
3.17.1
T1/J1 MODE
In T1/J1 mode, the Receive System Interface can be set in Non-
multiplexed Mode or Multiplexed Mode. In the Non-multiplexed Mode,
the RSDn pin is used to output the received data from each link at the bit
rate of 1.544 Mb/s or 2.048 Mb/s (T1/J1 mode E1 rate). While in the Mul-
tiplexed Mode, the received data from the two links is converted to 2.048
Mb/s format and byte interleaved to form one high speed data stream
and output on the MRSD pin at the bit rate of 8.192 Mb/s.
In the Receive Clock Master mode, the device outputs clock
(M)RSCKn/(M)RSFSn. This clock is derived from line side signal or
MCLK (When LOSS).
In the Receive Clock Master mode, if RSCKn outputs pulses during
the entire T1/J1 frame, the Receive System Interface is in Receive Clock
Master Full T1/J1 mode. If only the clocks aligned to the selected chan-
nels are output on RSCKn, the Receive System Interface is in Receive
Clock Master Fractional T1/J1 mode.
In the Receive Clock Slave mode, outside inputs clock (M)RSCKn/
(M)RSFSn to the device. To avoid shatter data, this clock should keep
the same source with line side. If the backplane data rate is 2.048 Mb/s,
means T1 mode E1 rate, the receive data(1.544 Mb/s) should be
mapped to 2.048 Mb/s,there are 3 kinds of mapping schemes.
In the Receive Multiplexed mode, since the received data from the
two links should be converted to 2.048 Mb/s format first and then multi-
plexed to 8.192 Mb/s, there are still 3 kinds of schemes to be selected.
Table 39 summarizes how to set the Receive System Interface of
each link into various operating modes and the pins’ direction of the
Receive System Interface in different operating modes.
3.17.1.1
Receive Clock Master Mode
In the Receive Clock Master mode, each link uses its own timing
signal on the RSCKn pin and framing pulse on the RSFSn pin to output
the data on each RSDn pin. The signaling bits on the RSIGn pin are per-
channel aligned with the data on the RSDn pin.
In the Receive Clock Master mode, the data on the system inter-
face is clocked by the RSCKn. The active edge of the RSCKn used to
update the pulse on the RSFSn is determined by the FE bit. The active
edge of the RSCKn used to update the data on the RSDn and RSIGn is
determined by the DE bit. If the FE bit and the DE bit are not equal, the
pulse on the RSFSn is ahead.
In the Receive Clock Master mode, the RSFSn can indicate each
F-bit or the first F-bit of every SF/ESF/T1 DM/SLC-96 multi-frame. In SF
format, the RSFSn can also indicate every second F-bit or the first F-bit
of every second SF multi-frame. All the indications are selected by the
CMFS bit and the ALTIFS bit. The active polarity of the RSFSn is
selected by the FSINV bit.
The Receive Clock Master mode includes two sub-modes: Receive
Clock Master Full T1/J1 mode and Receive Clock Master Fractional T1/
J1 mode.
3.17.1.1.1
Receive Clock Master Full T1/J1 Mode
Besides all the common functions described in the Receive Clock
Master mode, the special feature in this mode is that the RSCKn is a
standard 1.544 MHz clock, and the data in the F-bit and all 24 channels
in a standard T1/J1 frame are clocked out by the RSCKn.
Table 39: Operating Modes Selection In T1/J1 Receive Path
RMUX RMODE
G56K, GAP /
FBITGAP
MAP[1:0] 2
Operating Mode
Receive System Interface Pin
Input
Output
0
00 / 0
X
Receive Clock Master Full T1/J1
X
RSCKn, RSFSn,
RSDn, RSIGn
not all 0s 1
Receive Clock Master Fractional T1/J1
1X
00
Receive Clock Slave - T1/J1 Rate
RSCKn, RSFSn
RSDn, RSIGn
01
Receive Clock Slave - T1/J1 Mode E1 Rate per G.802
10
Receive Clock Slave - T1/J1 Mode E1 Rate per One Filler Every Four CHs
11
Receive Clock Slave - T1/J1 Mode E1 Rate per Continuous CHs
1X
X
01
Receive Multiplexed - T1/J1 Mode E1 Rate per G.802
MRSCK, MRSFS
MRSD, MRSIG
10
Receive Multiplexed - T1/J1 Mode E1 Rate per One Filler Every Four CHs
11
Receive Multiplexed - T1/J1 Mode E1 Rate per Continuous CHs
NOTE:
1. When the G56K, GAP bits in RPLC indirect registers are set, the PCCE bit must be set to ‘1’.
2. The MAP[1:0] bits can not be set to ‘00’ in the Receive Multiplexed mode.
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