參數(shù)資料
型號(hào)： IDT82P2282PF
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 342/381頁(yè)
文件大小： 0K
描述： TXRX T1/J1/E1 2CHAN 100-TQFP
標(biāo)準(zhǔn)包裝： 15
類型： 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 2/2
規(guī)程： T1/E1/J1
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x20）
包裝： 托盤
其它名稱： 82P2282PF
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
63
August 20, 2009
3.16
RECEIVE PAYLOAD CONTROL
Different test patterns can be inserted in the received data stream
or the received data stream can be extracted to the PRBS Generator/
Detector for test in this block.
To enable all the functions in the Receive Payload Control, the
PCCE bit must be set to ‘1’.
The following methods can be executed on the data to be output on
the RSDn/MRSD pins on a per-channel/per-TS basis or on a global
basis of the corresponding link (the methods are arranged from the high-
est to the lowest in priority):
- When the TESTEN bit is enabled and the PRBSDIR bit is ‘0’, the
received data will be extracted to the PRBS Generator/Detector. The
received data can be extracted in unframed mode, in 8-bit-based mode
or in 7-bit-based mode. This selection is made by the PRBSMODE[1:0]
bits. In unframed mode, all the received data stream is extracted and the
per-channel/per-TS configuration in the TEST bit is ignored. In 8-bit-
based mode or in 7-bit-based mode, the received data will only be
extracted on the channel/timeslot configured by the TEST bit. Refer to
- Selected by the GSUBST[2:0] bits, the data of all channels/
timeslots of the corresponding link will be replaced by the data trunk
code set in the DTRK[7:0] bits, or the milliwatt pattern defined in the
Table 36 and Table 37. When the GSUBST[2:0] bits are set to ‘000’,
these replacements will be performed on a per-channel/per-TS basis by
setting the SUBST[2:0] bits in the corresponding channel/timeslot.
- When the SIGFIX bit is set to ‘1’, the signaling bits (ABCD) will be
fixed to the value set in the POL bit. This function is only supported in
the SF, ESF and SLC-96 formats in T1/J1 mode.
- Invert the most significant bit, the even bits and/or the odd bits by
setting the SINV, OINV, EINV bits.
- When the TESTEN bit is enabled and the PRBSDIR bit is ‘1’, the
received data will be replaced by the test pattern generated from the
PRBS Generator/Detector. The received data can be replaced in
unframed mode, in 8-bit-based mode or in 7-bit-based mode. This selec-
tion is made by the PRBSMODE[1:0] bits. In unframed mode, all the
received data stream is replaced and the per-channel/per-TS configura-
tion in the TEST bit is ignored. In 8-bit-based mode or in 7-bit-based
mode, the received data will only be replaced on the channel/timeslot
configured by the TEST bit. Refer to Chapter 3.27.1 PRBS Generator /
Detector for details.
The following methods can be executed on the signaling bits to be
output on the RSIGn/MRSIG pins on a per-channel/per-TS basis or on a
global basis of the corresponding link (the methods are arranged from
the highest to the lowest in priority):
- Selected by the ABXX bit, the signaling bits can be valid in the
upper 2-bit positions of the lower nibble of each channel or in the lower
nibble of each channel. The other bits of the channel are Don’t Care
conditions. This function is only supported in T1/J1 mode ESF/SLC-96
format.
- Enabled by the SIGSNAP bit, the signaling snapshot will be exe-
cuted. The signaling snapshot means that the signaling bits of the first
basic frame are locked and output as the signaling bits of the current
whole multi-frame. This function is not supported in T1 DM format.
- Enabled by the GSTRKEN bit, the signaling bits (ABCD) of all
channels/timeslots of the corresponding link will be replaced by the sig-
naling trunk conditioning code in the A,B,C,D bits. When the GSTRKEN
bit is ‘0’, the replacement will be performed on a per-channel/per-TS
basis by setting the STRKEN bit in the corresponding channel/timeslot.
The indirect registers of the Receive Payload Control are accessed
by specifying the address in the ADDRESS[6:0] bits. Whether the data is
Table 36: A-Law Digital Milliwatt Pattern
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Byte 1
00
11
01
0
Byte 2
00
10
00
0
1
Byte 3
00
10
00
0
1
Byte 4
00
11
01
0
Byte 5
10
11
01
0
Byte 6
10
00
0
1
Byte 7
10
00
0
1
Byte 8
10
11
01
0
Table 37: -Law Digital Milliwatt Pattern
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Byte 1
0
01
11
1
0
Byte 2
0
00
10
1
Byte 3
0
00
10
1
Byte 4
0
01
11
1
0
Byte 5
1
0
01
11
1
0
Byte 6
1
0
00
10
1
Byte 7
1
0
00
10
1
Byte 8
1
0
01
11
1
0
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