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參數(shù)資料
| 型號： | IDT82P2282 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | Dual T1/E1/J1 Long Haul / Short Haul Transceiver |
| 中文描述： | 雙T1/E1/J1收發(fā)長途/短途收發(fā)器 |
| 文件頁數(shù)： | 79/375頁 |
| 文件大?。?/td> | 2430K |
| 代理商： | IDT82P2282 |
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IDT82P2281
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
68
October 7, 2003
3.20
FRAME GENERATOR
3.20.1
GENERATION
3.20.1.1
T1 / J1 Mode
In T1/J1 mode, the data to be transmitted can be generated as
Super-Frame (SF), Extended Super-Frame (ESF), T1 Digital Multiplexer
(DM) or Switch Line Carrier - 96 (SLC-96) format.
3.20.1.1.1
The SF is generated when the FDIS bit is ‘0’.
The Frame Alignment Pattern (‘100011011100’ for T1 /
‘10001101110X’ for J1) will replace the F-bit of each frame if the FDIS bit
is set to ‘0’. The F-bit of the 12th frame in J1 mode should be ‘0’ unless
Yellow alarm signal is transmitted.
When the FDIS bit is ‘0’, one Ft bit (the F-bit in odd frame, refer to
Table 12) will be inverted if the FtINV bit is set; one Fs bit (the F-bit in
even frame, refer to Table 12) will be inverted if the FsINV bit is set.
When the FDIS bit is ‘0’, configured by the MIMICEN bit, the mimic
pattern can be inserted into the bit right after each F-bit. The content of
the mimic pattern is the same as the F-bit. The mimic pattern insertion is
for diagnostic purpose.
The Yellow alarm signal will be manually inserted in the data
stream to be transmitted when the XYEL bit is set, or the Yellow alarm
signal will be inserted automatically by setting the AUTOYELLOW bit
when Red alarm is declared in the received data stream. The pattern
and the position of the Yellow alarm is different in T1 and J1 modes:
- In T1 mode, the Yellow alarm signal is logic 0 on the 2nd bit of
each channel;
- In J1 mode, the Yellow alarm signal is logic 1 on the 12th F-bit
position.
Super Frame (SF) Format
3.20.1.1.2
The ESF is generated when the FDIS bit is ‘0’.
The Frame Alignment Pattern (‘001011’) will replace the F-bit in
Frame (4n) (0<n<7) if the FDIS bit is set to ‘0’.
When the FDIS bit is ‘0’, one Frame Alignment bit (refer to Table 13
for its position) will be inverted if the FsINV bit is set.
When the FDIS bit and the CRCBYP bit are both ‘0’s, the calcu-
lated 6-bit CRC of the previous ESF frame will be inserted in the current
CRC-bit positions in every 4th frame starting with Frame 2 (refer to
Table 13) of the current ESF frame.
When the FDIS bit is ‘0’, all the 6 CRC bits will be inverted if the
CRCINV bit is set.
When the FDIS bit is ‘0’, the DL bit (refer to Table 13) can be
replaced with the Yellow alarm signal, the Bit-Oriented Code (refer to
Chapter 3.20.4 Bit-Oriented Message Transmitter (T1/J1 Only)), the
Automatic Performance Report Message (refer to Chapter 3.20.3 Auto-
matic Performance Report Message (T1/J1 Only)), the HDLC data (refer
to Chapter 3.20.2 HDLC Transmitter) or the idle code (‘FFFF’ for T1 /
‘FF7E’ for J1). The latter four kinds of replacements are enabled only if
the FDLBYP bit is set to ‘0’. When all of the five kinds of replacements
are enabled, the priority from highest to lowest is: Yellow alarm signal,
Extended Super Frame (ESF) Format
Bit-Oriented Code, Automatic Performance Report Message, HDLC
data and idle code.
The Yellow alarm signal will be manually inserted in the data
stream to be transmitted when the XYEL bit is set, or the Yellow alarm
signal will be inserted automatically by setting the AUTOYELLOW bit
when Red alarm is declared in the received data stream. The Yellow
alarm signal is transmitted in the DL bit position. Its pattern is ‘FF00’ in
T1 mode or ‘FFFF’ in J1 mode.
When the FDIS bit is ‘0’, configured by the MIMICEN bit, the mimic
pattern can be inserted into the bit right after each F-bit. The content of
the mimic pattern is the same as the F-bit. The mimic pattern insertion is
for diagnostic purpose.
3.20.1.1.3
The T1 DM is generated when the FDIS bit is ‘0’.
The Frame Alignment Pattern (‘100011011100’) will replace the F-
bit of each frame if the FDIS bit is set to ‘0’.
When the FDIS bit is ‘0’, one Ft bit (the F-bit in odd frame, refer to
Table 14) will be inverted if the FtINV bit is set; one Fs bit (the F-bit in
even frame, refer to Table 14) will be inverted if the FsINV bit is set.
When the FDIS bit is ‘0’, configured by the MIMICEN bit, the mimic
pattern can be inserted into the bit right after each F-bit. The content of
the mimic pattern is the same as the F-bit. The mimic pattern insertion is
for diagnostic purpose.
When the FDIS bit is ‘0’, the DDS pattern (‘0XX11101’) will replace
the Bit 8 & 5~1 of each Channel 24 (refer to Table 14).
When the FDIS bit is ‘0’, all the 6 DDS pattern bits will be inverted if
the DDSINV bit is set.
The ‘D’ bit in Bit 7 of each Channel 24 can be replaced with the
HDLC data when the FDIS bit and the FDLBYP bit are both ‘0’s. (Refer
to Chapter 3.20.2 HDLC Transmitter for details).
The Yellow alarm signal will be manually inserted in the data
stream to be transmitted when the XYEL bit is set, or the Yellow alarm
signal will be inserted automatically by setting the AUTOYELLOW bit
when Red alarm is declared in the received data stream. The Yellow
alarm signal is ‘0’ transmitted in the ‘Y’ bit in Bit 6 of each Channel 24.
The ‘Y’ bit should be ‘1’ when there is no Yellow alarm signal to be trans-
mitted.
T1 Digital Multiplexer (DM) Format (T1 only)
3.20.1.1.4
The SLC-96 is generated when the FDIS bit is ‘0’.
The Frame Alignment Pattern (‘001000110111001000110111’), the
Spoiler Bit and all the other Ft bits (the F-bit in odd frame) will replace
their F-bit (refer to Table 15 for their values and positions) if the FDIS bit
is set to ‘0’.
When the FDIS bit is ‘0’, one Synchronization Fs bit will be inverted
if the FsINV bit is set; one Ft bit will be inverted if the FtINV bit is set.
When the FDIS bit and the FDLBYP bit are both ‘0’s, the contents
in the XDL0, XDL1 & XDL2 registers will replace the Concentrator (C)
bits, the Maintenance (M) bits, the Alarm (A) bits and the Switch (S) bits
respectively (refer to Table 15).
When the FDIS bit is ‘0’, configured by the MIMICEN bit, the mimic
pattern can be inserted into the bit right after each F-bit. The content of
Switch Line Carrier - 96 (SLC-96) Format (T1 only)
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