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IDT82P2281
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Pin Description
17
August 20, 2009
TSCK / MTSCK Output / Input
56
TSCK: Transmit Side System Clock
In Transmit Clock Master mode, TSCK outputs a (gapped) 1.544 MHz (for T1/J1 mode) / 2.048 MHz (for E1 mode) clock
used to sample the signal on the TSD and TSIG pins and update the signal on the TSFS pin.
In Transmit Clock Slave mode, TSCK inputs a 1.544 MHz (for T1/J1 mode only), 2.048 MHz or 4.096 MHz clock used to
sample the signal on the TSD, TSIG and TSFS pins.
MTSCK: Multiplexed Transmit Side System Clock
In Transmit Multiplexed mode, MTSCK inputs a 8.192 MHz or 16.384 MHz clock used to sample the signal on the MTSD,
MTSIG and MTSFS pins.
TSCK/MTSCK is a Schmitt-triggered input/output with pull-up resistor.
Clock Generator
OSCI
Input
75
OSCI: Crystal Oscillator Input
This pin is connected to an external clock source.
The clock frequency of OSCI is defined by CLK_SEL[2:0]. The clock accuracy should be ±32 ppm and duty cycle should
be from 40% to 60%.
Hardware or software reset can only be applied when the clock on this pin is available.
OSCO
Output
74
OSCO: Crystal Oscillator Output
This pin outputs the inverted, buffered clock input from OSCI.
CLK_SEL[0]
CLK_SEL[1]
CLK_SEL[2]
Input
65
66
67
CLK_SEL[2:0]: Clock Selection
These three pins select the input clock signal:
When the CLK_SEL[2] pin is low, the input clock signal is N X 1.544 MHz;
When the CLK_SEL[2] pin is high, the input clock signal is N X 2.048 MHz.
When the CLK_SEL[1:0] pins are ‘00’, the N is 1;
When the CLK_SEL[1:0] pins are ‘01’, the N is 2;
When the CLK_SEL[1:0] pins are ‘10’, the N is 3;
When the CLK_SEL[1:0] pins are ‘11’, the N is 4.
CLK_SEL[2:0] are Schmitt-trigger inputs.
CLK_GEN
Output
61
CLK_GEN: Clock Generator
This pin outputs the 1.544/2.048 MHz clock signal generated by the Clock Generator.
REFA_OUT
Output
70
REFA_OUT: Reference Clock Output A
The frequecy is 2.048 MHz(E1) or 1.544 MHz(T1/J1).
When no LOS is detected, this pin outputs a recovered clock from the Clock and Data Recovery function block.
When LOS is detected, this pin outputs MCLK or high level, as selected by the REFH_LOS bit (b0, T1/J1-03EH/ b0, E1-
03EH).
Note: MCLK is a clock derived from OSCI using an internal PLL, the frequency is 2.048 MHz(E1) or 1.544 MHz(T1/J1).
Control Interface
RESET
Input
64
RESET: Reset (Active Low)
A low pulse for more than 100 ns on this pin resets the device. All the registers are accessible 2 ms after the reset.
Reset can only be applied when the clock on the OSCI pin is available.
The RESET pin is a Schmitt-trigger input with a weak pull-up resistor.
GPIO
Output / Input
1
General Purpose I/O
This pin can be defined as input pin or output pin by the DIR0 bit (b0, T1/J1-006H / b0, E1-006H). When the pin is input,
its polarity is indicated by the LEVEL0 bit (b2, T1/J1-006H / b2, E1-006H). When the pin is output, its polarity is controlled
by the LEVEL0 bit (b2, T1/J1-006H / b2, E1-006H).
GPIO is a Schmitt-trigger input/output with a pull-up resistor
THZ
Input
2
THZ: Transmit High-Z
A high level on this pin puts the TTIP/TRING pins into high impedance state.
THZ is a Schmitt-trigger input.
Name
Type
Pin No.
Description