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參數(shù)資料
| 型號： | IDT7MMV4101S12BG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | Octal Buffers/Drivers With 3-State Outputs 20-PDIP -40 to 85 |
| 中文描述： | 128K X 24 STANDARD SRAM, 12 ns, PBGA119 |
| 封裝： | PLASTIC, BGA-119 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 86K |
| 代理商： | IDT7MMV4101S12BG |
6.42
IDT7MMV4101
128K x 24 Three Megabit 3.3V CMOS Static RAM Commercial and Industrial Temperature Ranges
5
Timing Waveform of Read Cycle No. 1
(1)
Timing Waveform of Read Cycle No. 2
(1,2,4)
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Device is continuously selected,
CS
is LOW.
3. Address must be valid prior to or coincident with the later of
CS
transition LOW; otherwise t
AA
is the limting parameter.
4.
OE
is LOW.
5. Transition is measured ±200mV fromsteady state.
DATA
OUT
ADDRESS
4083 drw 05
t
RC
t
AA
t
OH
t
OH
DATA
OUT
VALID
PREVIOUS DATA
OUT
VALID
.
ADDRESS
4083 drw 04
OE
CS
DATA
OUT
(5)
(5)
(5)
(5)
DATA
OUT
VALID
HIGH IMPEDANCE
t
AA
t
RC
t
OE
t
ACS
t
OLZ
t
CHZ
t
CLZ
(3)
t
OHZ
.
,
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