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參數(shù)資料
| 型號： | IDT7MMV4101S12BG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | Octal Buffers/Drivers With 3-State Outputs 20-PDIP -40 to 85 |
| 中文描述： | 128K X 24 STANDARD SRAM, 12 ns, PBGA119 |
| 封裝： | PLASTIC, BGA-119 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大小： | 86K |
| 代理商： | IDT7MMV4101S12BG |
4
IDT7MMV4101
128K x 24 Three Megabit 3.3V CMOS Static RAM Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(2)
(V
CC
= 3.3V ±10%)
-10
(3)
-12
-15
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle
t
RC
Read Cycle Time
10
____
12
____
15
____
ns
t
AA
Address Access Time
____
10
____
12
____
15
ns
t
ACS
Chip Select Access Time
____
10
____
12
____
15
ns
t
CLZ
(1)
Chip Select to Output in Low-Z
3
____
3
____
3
____
ns
t
OE
Output Enable to Output Valid
____
4
____
6
____
7
ns
t
OLZ
(1)
Output Enable to Output in Low-Z
0
____
0
____
0
____
ns
t
CHZ
(1)
Chip Deselect to Output in High-Z
____
5
____
6
____
7
ns
t
OHZ
(1)
Output Disable to Output in High-Z
____
5
____
6
____
7
ns
t
OH
Output Hold fromAddress Change
3
____
3
____
3
____
ns
t
PU
(1)
Chip Select to Power-Up Time
0
____
0
____
0
____
ns
t
PD
(1)
Chip Deselect to Power-Down Time
____
10
____
12
____
15
ns
Write Cycle
t
WC
Write Cycle Time
10
____
12
____
15
____
ns
t
CW
Chip Select to End-of-Write
8
____
10
____
12
____
ns
t
AW
Address Valid to End-of-Write
8
____
10
____
12
____
ns
t
AS
Address Set-up Time
0
____
0
____
0
____
ns
t
WP
Write Pulse Width
8
____
10
____
12
____
ns
t
WR
Write Recovery Time
0
____
0
____
0
____
ns
t
WHZ
(1)
Write Enable to Output in High-Z
____
5
____
5
____
5
ns
t
DW
Data to Write Time Overlap
6
____
6
____
7
____
ns
t
DH
Data Hold fromWrite Time
0
____
0
____
0
____
ns
t
OW
(1)
Output Active fromEnd-of-Write
3
____
3
____
3
____
ns
4083 tbl 09
NOTES:
1. This parameter is guaranteed by design but not tested.
2. These specifications are for the individual 71V124 Static RAMs.
3. Commercial temperature only, V
CC
= -5% to +10%.
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