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參數(shù)資料
| 型號(hào)： | IDT7M1024S25G |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | Octal Buffers/Drivers With 3-State Outputs 20-SOIC -40 to 85 |
| 中文描述： | 8K X 18 MULTI-PORT DEVICE SRAM MODULE, 25 ns, CPGA142 |
| 封裝： | CERAMIC, PGA-142 |
| 文件頁(yè)數(shù)： | 7/8頁(yè) |
| 文件大?。?/td> | 113K |
| 代理商： | IDT7M1024S25G |
7.4
7
IDT7M1024
4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
NOTES:
1. During dead cycle, if
CE
is LOW, data will be written into array.
2.
OE
LOW throughout.
TIMING WAVEFORM OF READ-TO-WRITE CYCLE NO. 1,
CE
LOW
(1,2)
R/
W
ADDRESS
DATA
IN
CE
CLKEN
CLOCK
2809 drw 09
DATA
OUT
An
An + 1
An + 1
An + 2
t
CLK
t
CLKH
t
CLKL
t
RHD
t
CLZ
t
RSU
Dn + 1
Dn + 2
Qn
t
CQV
t
CHZ
TIMING WAVEFORM OF READ-TO-WRITE CYCLE No. 1, CE HIGH
(1)
R/
W
ADDRESS
DATA
IN
CE
CLKEN
CLOCK
2809 drw 08
An
An + 1
An + 2
An + 3
t
CLK
t
CLKH
t
CLKL
t
RHD
t
CLZ
t
CLK
t
CLKH
t
CLKL
t
RSU
Dn + 2
Dn + 3
Qn
t
CQV
t
CHZ
DATA
OUT
NOTE:
1.
OE
LOW throughout.
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