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參數(shù)資料
| 型號： | IDT7M1024S25G |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | Octal Buffers/Drivers With 3-State Outputs 20-SOIC -40 to 85 |
| 中文描述： | 8K X 18 MULTI-PORT DEVICE SRAM MODULE, 25 ns, CPGA142 |
| 封裝： | CERAMIC, PGA-142 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 113K |
| 代理商： | IDT7M1024S25G |
7.4
5
IDT7M1024
4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Figure 1. Output Load
Figure 3. Lumped Capacitive Load, Typical Derating
Figure 2. Output Load (for t
CLZ
, t
CHZ
, t
OLZ
, and t
OHZ
)
*Including scope and jig.
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE RANGE —
(READ AND WRITE CYCLE TIMING)
(Commercial: V
CC
= 5V
±
10%, T
A
= 0
°
C to +70
°
C; Military: V
CC
= 5V
±
10%, T
A
= –55
°
C to +125
°
C)
7M1024SxxG, 7M1024SxxGB
–20
–25
Min. Max.
Min. Max. Min. Max.
20
—
25
8
—
10
8
—
10
—
20
—
5
—
6
2
—
2
3
—
3
2
—
2
2
9
2
—
10
—
0
—
0
—
9
—
5
—
6
3
—
3
–30
Symbol
t
CLK
t
CLKH
t
CLKL
t
CQV
t
RSU
t
RHD
t
COH
t
CLZ
t
CHZ
t
OE
t
OLZ
t
OHZ
t
CSU
t
CHD
Port-to-Port Delay
t
CWDD
Parameter
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Clock HIGH to Output Valid
Registered Signal Set-up Time
Registered Signal Hold Time
Data Output Hold After Clock HIGH
Clock HIGH to Output Low-Z
Clock HIGH to Output High-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
Output Disable to Output High-Z
Clock Enable, Disable Set-up Time
Clock Enable, Disable Hold Time
—
—
—
25
—
—
—
—
12
12
—
11
—
—
30
12
12
—
7
2
3
2
2
—
0
—
7
3
—
—
—
30
—
—
—
—
15
15
—
14
—
—
Write Port Clock HIGH to Read Data Delay
—
35
—
45
—
55
ns
2809 tbl 11
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figures 1, 2 and 3
2909 tbl 10
DATA
OUT
1.5V
50
Zo = 50
2809 drw 03
1250
5pF*
775
5V
DATA
OUT
2809 drw 04
1
2
3
4
5
6
7
8
20 40
100
60 80
Capacitance (pF)
120140 160 180 200
TAA
(Typical, ns)
2809 drw 05
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