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參數(shù)資料
| 型號： | IDT7M1003S50C |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 128K x 8 64K x 8 CMOS DUAL-PORT STATIC RAM MODULE |
| 中文描述： | 64K X 8 MULTI-PORT DEVICE SRAM MODULE, 50 ns, DMA64 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 171K |
| 代理商： | IDT7M1003S50C |
7.5
4
IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(V
CC
=5.0V
±
10%, T
A
= –55
°
C to +125
°
C and 0
°
C to +70
°
C)
IDT7M1001
Min.
IDT7M1003
Min.
Symbol
Parameter
Test Conditions
Max.
Max.
Unit
|I
LI
|
Input Leakage
(Address, Data & Other Controls)
V
CC
= Max.
V
IN
= GND to V
CC
—
80
—
40
μ
A
|I
LI
|
Input Leakage
(
CS
and
SEM
)
V
CC
= Max.
V
IN
= GND to V
CC
—
10
—
10
μ
A
|I
LO
|
Output Leakage
(Data)
V
CC
= Max.
CS
≥
V
IH,
V
OUT
= GND to V
CC
—
80
—
40
μ
A
V
OL
Output Low Voltage
V
CC
= Min. I
OL
= 4mA
—
0.4
—
0.4
V
V
OH
Output High Voltage
V
CC
= Min. I
OH
= –4mA
2.4
—
2.4
—
V
2804 tbl 07
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
2804 tbl 08
*Including scope and jig.
+5 V
30 pF*
DATA
OUT
480
255
2804 drw 04
+5 V
5 pF*
DATA
OUT
480
255
2804 drw 05
Figure 2. Output Load
(for t
CLZ
, t
CHZ
, t
OLZ
. t
OHZ
, t
WHZ
, t
OW
)
Figure 1. Output Load
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