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參數(shù)資料
| 型號(hào)： | IDT7M1002S40G |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE |
| 中文描述： | 16K X 32 MULTI-PORT DEVICE SRAM MODULE, 40 ns, PMA121 |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大?。?/td> | 166K |
| 代理商： | IDT7M1002S40G |
7.02
4
IDT7M1002
16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
2795 tbl 08
Figure 1. Output Load
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
5ns
1.5V
1.5V
See Figures 1 and 2
CAPACITANCE
(1)
(T
A
= +25
°
C, f = 1.0MHz)
Symbol
C
IN (1)
Parameter
Input Capacitance
(
CS
,
OE
,
SEM
, Address)
Input Capacitance
(R/
W
,
I/O
,
INT
)
Input Capacitance
(
BUSY
, M/
S
)
Output Capacitance
(I/O)
Condition
V
IN
= 0V
Max.
40
Unit
pF
C
IN(2)
V
IN
= 0V
12
pF
C
IN(3)
V
IN
= 0V
45
pF
C
OUT
V
OUT
= 0V
12
pF
NOTE:
1. This parameter is guaranteed by design but not tested.
(Continued on next page)
*Including scope and jig capacitances.
2795 drw 04
+5V
480
255
5pF*
DATA
OUT
*Including scope and jig capacitances.
2795 drw 03
+5V
480
255
30pF*
BUSY, INT
Figure 2. Output Load
(For t
CHZ
, t
CLZ
, t
OHZ
, t
OLZ
, t
WHZ
, t
OW)
2795 tbl 07
2795 tbl 09
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5V
±
10%, T
A
= –55
°
C to +125
°
C or 0
°
C to +70
°
C)
7M1002SxxG
7M1002SxxGB
–40
30
–35
–45
Symbol
Read Cycle
t
RC
t
AA
t
ACS
(2)
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
Address Access Time
Chip Select Access Time
30
—
—
—
30
30
35
—
—
—
35
35
40
—
—
—
40
40
45
—
—
—
45
45
ns
ns
ns
t
OE
t
OH
t
LZ
(1)
t
HZ
(1)
t
PU
(1)
t
PD
(1)
t
SOP
Output Enable Access Time
Output Hold from Address Change
Output to Low-Z
—
3
3
17
—
—
—
3
3
20
—
—
—
3
3
22
—
—
—
3
5
25
—
—
ns
ns
ns
Output to High-Z
—
15
—
15
—
17
—
20
ns
Chip Select to Power Up Time
Chip Deselect to Power Up Time
Sem. Flag Update Pulse (
OE
or
SEM
)
0
—
15
—
50
—
0
—
15
—
50
—
0
—
15
—
50
—
0
—
15
—
50
—
ns
ns
ns
Write Cycle
t
WC
t
CW
(2)
Write Cycle Time
Chip Select to End-of-Write
30
25
—
—
35
30
—
—
40
35
—
—
45
40
—
—
ns
ns
t
AW
t
AS
t
WP
t
WR
Address Valid to End-of-Write
Address Set-Up Time
Write Pulse Width
Write Recovery Time
25
0
25
0
—
—
—
—
30
0
30
0
—
—
—
—
35
0
35
0
—
—
—
—
40
0
35
0
—
—
—
—
ns
ns
ns
ns
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