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參數(shù)資料
| 型號： | IDT7M1002S35G |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE |
| 中文描述： | 16K X 32 MULTI-PORT DEVICE SRAM MODULE, 35 ns, CPGA121 |
| 封裝： | CERAMIC, PGA-121 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 166K |
| 代理商： | IDT7M1002S35G |
IDT7M1002
16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
7.02
5
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5V
±
10%, T
A
= 55
°
C to +125
°
C or 0
°
C to +70
°
C)
7M1002SxxG
7M1002SxxGB
–40
Min.
Max.
30
–35
–45
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
2795 tbl 10
Write Cycle (continued)
t
DW
Data Valid to End-of-Write
t
DH
Data Hold Time
t
HZ
(1)
Output to High-Z
t
OW
(1)
Output Active from End-of-Write
22
0
—
—
25
0
—
—
25
0
—
—
25
0
—
—
ns
ns
—
0
15
—
—
0
15
—
—
0
17
—
—
0
20
—
ns
ns
t
SWRD
t
SPS
Busy Cycle-Master Mode
(3)
SEM
Flag Write to Read Time
SEM
Flag Contention Window
10
10
—
—
10
10
—
—
10
10
—
—
10
10
—
—
ns
ns
t
BAA
t
BDA
t
BAC
t
BDC
t
WDD
(5)
BUSY
Access Time to Address
BUSY
Disable Time to Address
BUSY
Access Time to Chip Select
BUSY
Disable Time to Chip Deselect
Write Pulse to Data Delay
—
—
—
—
—
30
25
25
25
55
—
—
—
—
—
35
30
30
25
60
—
—
—
—
—
35
30
30
25
65
—
—
—
—
—
35
30
30
25
70
ns
ns
ns
ns
ns
t
DDD
t
APS
(6)
Write Data Valid to Read Data Delay
Arbitration Priority Set-Up Time
—
5
40
—
—
5
45
—
—
5
50
—
—
5
55
—
ns
ns
t
BDD
Busy Cycle-Slave Mode
(4)
t
WB
(7)
Write to BUSY Input
t
WH
(8)
Write Hold after BUSY
t
WDD
(5)
Write Pulse to Data Delay
Interrupt Timing
t
AS
Address Set-Up Time
t
WR
Write Recovery Time
t
INS
Interrupt Set Time
t
INR
Interrupt Reset Time
BUSY
Disable to Valid Time
—
NOTE 9
—
NOTE 9
—
NOTE 9
—
NOTE 9
ns
0
—
0
—
0
—
0
—
ns
25
—
—
55
25
—
—
60
25
—
—
65
25
—
—
70
ns
ns
0
0
—
—
—
—
25
25
0
0
—
—
—
—
30
30
0
0
—
—
—
—
32
32
0
0
—
—
—
—
35
35
ns
ns
ns
ns
NOTES:
1. This parameter is guaranteed by design but not tested.
2. To access RAM,
CS
≤
V
IL
and
SEM
≥
V
IH
. To access semaphore,
CS
≥
V
IH
and
SEM
≤
V
IL
.
3. When the module is being used in the Master Mode (M/
S
≥
V
IH
).
4. When the module is being used in the Slave Mode (M/
S
≤
V
IL
).
5. Port-to-Port delay through the RAM cells from the writing port to the reading port.
6. To ensure that the earlier of the two ports wins.
7. To ensure that the write cycle is inhibited during contention.
8. To ensure that a write cycle is completed after contention.
9. tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual), or tDDD - tWP (actual).
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