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參數(shù)資料
| 型號(hào)： | IDT7M1002S30G |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE |
| 中文描述： | 16K X 32 MULTI-PORT DEVICE SRAM MODULE, 30 ns, CPGA121 |
| 封裝： | CERAMIC, PGA-121 |
| 文件頁(yè)數(shù)： | 11/12頁(yè) |
| 文件大小： | 166K |
| 代理商： | IDT7M1002S30G |
IDT7M1002
16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
7.02
11
TIMING WAVEFORM OF INTERRUPT CYCLE
(1)
2795 drw 16
ADDR "A"
t
AS(3)
t
WR(4)
t
INS(3)
INTERRUPT SET ADDRESS
(2)
t
WC
CE
"A"
INT
"B"
R/
W
1"A"
2795 drw 17
ADDR "B"
t
AS(3)
t
INR(3)
INTERRUPT CLEAR ADDRESS
(2)
t
RC
CE
"B"
OE
"B"
INT
"B"
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt truth table.
3. Timing depends on which enable signal is asserted last.
4. Timing depends on which enable signal is de-asserted first.
TRUTH TABLE II: Semaphore Read/Write Control
Inputs
(2)
Outputs
I/O
Data_OUT
Data_IN
—
Mode
CS
R/
W
H
OE
SEM
Description
Read Data in Semaphore Flag
Write Data_IN (0, 8, 16, 24)
Not Allowed
H
H
L
L
X
X
L
L
L
X
2795 tbl 14
2795 tbl 13
TRUTH TABLE I: Non-Contention Read/Write Control
(1)
Inputs
Outputs
I/O
High-Z
Data_In
Data_OUT
High-Z
Mode
CS
R/W
X
L
H
X
OE
SEM
Description
Deselected or Power Down
Write
Read
Outputs Disabled
H
L
L
X
X
X
L
H
H
H
H
X
NOTE:
1. The conditions for non-contention are L_A (0–13)
≠
R_A (0–13).
2.
denotes a LOW to HIGH waveform transition.
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