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參數(shù)資料
| 型號： | IDT7M1002 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE |
| 中文描述： | 16K的× 32的CMOS雙端口靜態(tài)RAM模塊 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 166K |
| 代理商： | IDT7M1002 |
IDT7M1002
16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
7.02
7
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CS
CONTROLLED TIMING)
(1, 2, 4)
2795 drw 07
DATA
OUT
t
AW
t
DW
DATA
IN
CS
OE
ADDRESS
t
WC
t
DH
t
CHZ
t
AS(6)
t
WP(2)
t
WR(7)
t
WHZ
(9)
OW
t
(9)
(4)
(4)
DATA VALID
R/
W
(9)
2795 drw 08
t
AW
t
DW
DATA
IN
R/
W
CS
ADDRESS
t
WC
t
DH
t
AS(6)
t
WP(2)
t
WR(7)
DATA VALID
NOTES:
1. R/
W
must be HIGH during all address transitions.
2. A write occurs during the overlap (t
WP
) of a LOW
CS
and a LOW R/
W
.
3. t
WR
is measured from the earlier of
CS
or R/
W
(or
SEM
or R/
W
) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must be applied.
5. If the
CS
or
SEM
low transition occurs simultaneously with or after the R/
W
low transition, the outputs remain in the high impedance state.
6. Timing depends on which enable signal is asserted last.
7. Timing depends on which enable signal is de-asserted first.
8. If
OE
is LOW during a R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to
turn off and data to be placed on the bus for the required t
DW
. If
OE
is HIGH during an R/
W
controlled write cycle, this requirement does
not apply and the write pulse can be as short as the specified t
WP
.
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (R/
W
CONTROLLED TIMING)
(1, 2, 4)
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