參數(shù)資料
型號(hào)： IDT79RC32T355150DPI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 150 MHz, RISC MICROCONTROLLER, PQFP208
封裝： 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, QFP-208
文件頁數(shù)： 1/46頁
文件大?。?/td> 562K
代理商： IDT79RC32T355150DPI
1 of 46
June 8, 2001
2001 Integrated Device Technology, Inc.
*Notice: The information in this document is subject to change without notice
DSC 5900
Features List
N
RC32300 32-bit Microprocessor
– Enhanced MIPS-II ISA
– Enhanced MIPS-IV cache prefetch instruction
– DSP Instructions
– MMU with 16-entry TLB
– 8kB Instruction Cache, 2-way set associative
– 2kB Data Cache, 2-way set associative
– Per line cache locking
– Write-through and write-back cache management
– Debug interface through the EJTAG port
– Big or Little endian support
N
Interrupt Controller
– Allows status of each interrupt to be read and masked
N
I2C
– Flexible I2C standard serial interface to connect to a variety of
peripherals
– Standard and fast mode timing support
– Configurable 7 or 10-bit addressable slave
N
UARTs
– Two 16550 Compatible UARTs
– Baud rate support up to 115 kbits
N
Counter/Timers
– Three general purpose 32-bit counter/timers
N
General Purpose I/O Pins (GPIOP)
– 36 individually programmable pins
– Each pin programmable as input, output, or alternate function
– Input can be an interrupt or NMI source
– Input can also be active high, active low, or edge triggered
N
SDRAM Controller
– 2 memory banks, non-interleaved, 512 MB total
– 32-bit wide data path
– Supports 4-bit, 8-bit, and 16-bit wide SDRAM chips
– SODIMM support
– Stays on page between transfers
– Automatic refresh generation
N
Peripheral Device Controller
– 26-bit address bus
– 32-bit data bus with variable width support of 8-,16-, or 32-bits
– 8-bit boot ROM support
– 6 banks available, up to 64MB per bank
– Supports Flash ROM, PROM, SRAM, dual-port memory, and
peripheral devices
– Supports external wait-state generation, Intel or Motorola style
– Write protect capability
– Direct control of optional external data transceivers
N
System Integrity
– Programmable system watchdog timer resets system on time-
out
– Programmable bus transaction times memory and peripheral
transactions and generates a warm reset on time-out
N
DMA
– 16 DMA channels
– Services on-chip and external peripherals
– Supports memory-to-memory, memory-to-I/O, and I/O-to-I/O
transfers
– Supports flexible descriptor based operation and chaining via
linked lists of records (scatter / gather capability)
– Supports unaligned transfers
– Supports burst transfers
B
Block Diagram
lock Diagram
Figure 1 RC32355 Internal Block Diagram
Utopia 1 / 2
single or
dual DPI
RC32300
CPU Core
Interrupt
Controller
Watchdog
Timer
D. Cache
I. Cache
MMU
EJTAG
Arbiter
16 Channel
DMA
Controller
2 UARTS
(16550)
3 Counter
Timers
I2C
Controller
SDRAM &
Device
Controller
10/100
Ethernet
Interface
ATM
Interface
TDM
Interface
USB
Interface
GPIO
Interface
IP Bus
TDM Bus
Memory &
Peripheral
Bus
I2C Bus
Ch. 1
Ch. 2
GPIO Pins
MII
USB
Ext. Bus
Master
ICE
Serial
Channels
79RC32355
Preliminary Information*
Integrated Communications
Processor
相關(guān)PDF資料
PDF描述
IDT79RC32V332-100DH 32-BIT, 100 MHz, RISC MICROCONTROLLER, PQFP208
IDT79RC32V334-133BB9 32-BIT, 133 MHz, RISC MICROCONTROLLER, PBGA256
IDT79RC32V334-100BBI 32-BIT, 100 MHz, RISC MICROCONTROLLER, PBGA256
IDT79RC32V334-133BB8 32-BIT, 133 MHz, RISC MICROCONTROLLER, PBGA256
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