參數(shù)資料
型號: IDT79RC32V332-100DH
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 100 MHz, RISC MICROCONTROLLER, PQFP208
封裝: 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, QFP-208
文件頁數(shù): 1/27頁
文件大小: 295K
代理商: IDT79RC32V332-100DH
1 of 27
November 1, 2001
2001 Integrated Device Technology, Inc.
DSC 5914
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
RISCoreTM 32300 Family
Integrated Processor
Features
x
RC32300 32-bit Microprocessor
– Up to 133 MHz operation
– Enhanced MIPS-II Instruction Set Architecture (ISA)
– Cache prefetch instruction
– Conditional move instruction
– DSP instructions
– Supports big or little endian operation
– MMU with 32 page TLB
– 8kB Instruction Cache, 2-way set associative
– 2kB Data Cache, 2-way set associative
– Cache locking per line
– Programmable on a page basis to implement a write-through
no write allocate, write-through write allocate, or write-back
algorithms for cache management
– Compatible with a wide variety of operating systems
x
Local Bus Interface
– Up to 66 MHz operation
– 23-bit address bus
– 32-bit data bus
– Direct control of local memory and peripherals
– Programmable system watch-dog timers
– Big or little endian support
x
Interrupt Controller simplifies exception management
x
Four general purpose 32-bit timer/counters
x
Programmable I/O (PIO)
– Input/Output/Interrupt source
– Individually programmable
x
SDRAM Controller (32-bit memory only)
– 4 banks, non-interleaved
– Up to 256MB total SDRAM memory supported
– Implements full, direct control of discrete, SODIMM, or DIMM
memories
– Supports 16Mb through 256Mb SDRAM device depths
– Automatic refresh generation
x
Serial Peripheral Interface (SPI) master mode interface
x
UART Interface
– 16550 compatible UART
– Baud rate support up to 1.5M
x
Memory & Peripheral Controller
– 6 banks, up to 8MB per bank
– Supports 8-,16-, and 32-bit interfaces
– Supports Flash ROM, SRAM, dual-port memory, and
peripheral devices
– Supports external wait-state generation
– 8-bit boot PROM support
– Flexible I/O timing protocols
Block Diagram
Figure 1 RC32332 Block Diagram
Local
Memory/IO
Control
Interrupt Control
DMA Control
UART
32-bit Timers
SPI Control
Programmable I/O
PCI Bridge
IDT
Peripheral
Bus
RISCore 32300
Enhanced MIPS-II ISA
Integer CPU
RC5000
Compatible
CP0
32-page
TLB
EJTAG
In-Circuit Emulator Interface
2kB
2-set, Lockable
Data Cache
8kB
2-set
Lockable
Instr. Cache
IPBus
Bridge
SDRAM
Control
79RC32332
相關(guān)PDF資料
PDF描述
IDT79RC32V334-133BB9 32-BIT, 133 MHz, RISC MICROCONTROLLER, PBGA256
IDT79RC32V334-100BBI 32-BIT, 100 MHz, RISC MICROCONTROLLER, PBGA256
IDT79RC32V334-133BB8 32-BIT, 133 MHz, RISC MICROCONTROLLER, PBGA256
IDT79RC32V334-150BB9 32-BIT, 150 MHz, RISC MICROCONTROLLER, PBGA256
IDT79RC32V334-133BBI9 32-BIT, 133 MHz, RISC MICROCONTROLLER, PBGA256
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