參數(shù)資料
型號(hào): IDT79RC32H435-300BC
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 50/53頁(yè)
文件大小: 0K
描述: IC MPU 32BIT CORE 300MHZ 256-BGA
標(biāo)準(zhǔn)包裝: 90
系列: Interprise™
處理器類型: MIPS32 32-位
速度: 300MHz
電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-CABGA(17x17)
包裝: 托盤
其它名稱: 79RC32H435-300BC
6 of 53
January 19, 2006
IDT 79RC32435
PCILOCKN
I/O
PCI Lock. This signal is asserted by an external bus master to indicate that an
exclusive operation is occurring.
PCIPAR
I/O
PCI Parity. Even parity of the PCIAD[31:0] bus. Driven by the bus master during
address and write Data phases. Driven by the bus target during the read data
phase.
PCIPERRN
I/O
PCI Parity Error. If a parity error is detected, this signal is asserted by the
receiving bus agent 2 clocks after the data is received.
PCIREQN[3:0]
I/O
PCI Bus Request.
In PCI host mode with internal arbiter:
These signals are inputs whose assertion indicates to the internal RC32435
arbiter that an agent desires ownership of the PCI bus.
In PCI host mode with external arbiter:
PCIREQN[0]: asserted by the RC32435 to request ownership of the PCI bus.
PCIREQN[3:1]: unused and driven high.
In PCI satellite mode:
PCIREQN[0]: this signal is asserted by the RC32435 to request use of the PCI
bus.
PCIREQN[1]: function changes to PCIIDSEL and is used as a chip select during
configuration read and write transactions.
PCIREQN[3:2]: unused and driven high.
PCIRSTN
I/O
PCI Reset. In host mode, this signal is asserted by the RC32435 to generate a
PCI reset. In satellite mode, assertion of this signal initiates a warm reset.
PCISERRN
I/O
PCI System Error. This signal is driven by an agent to indicate an address par-
ity error, data parity error during a special cycle command, or any other system
error. Requires an external pull-up.
PCISTOPN
I/O
PCI Stop. Driven by the bus target to terminate the current bus transaction. For
example, to indicate a retry.
PCITRDYN
I/O
PCI Target Ready. Driven by the bus target to indicate that the current data can
complete.
General Purpose Input/Output
GPIO[0]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: U0SOUT
Alternate function: UART channel 0 serial output.
GPIO[1]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: U0SINP
Alternate function: UART channel 0 serial input.
GPIO[2]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: U0RTSN
Alternate function: UART channel 0 request to send.
GPIO[3]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: U0CTSN
Alternate function: UART channel 0 clear to send.
Signal
Type
Name/Description
Table 1 Pin Description (Part 3 of 6)
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IDT79RC32H435-300BCG 功能描述:IC MPU 32BIT CORE 300MHZ 256-BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:Interprise™ 標(biāo)準(zhǔn)包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點(diǎn):- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應(yīng)商設(shè)備封裝:516-PBGAPGE(27x27) 包裝:托盤
IDT79RC32H435-300BCGI 功能描述:IC MPU 32BIT CORE 300MHZ 256-BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:Interprise™ 標(biāo)準(zhǔn)包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點(diǎn):- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應(yīng)商設(shè)備封裝:516-PBGAPGE(27x27) 包裝:托盤
IDT79RC32H435-300BCI 功能描述:IC MPU 32BIT CORE 300MHZ 256-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:Interprise™ 標(biāo)準(zhǔn)包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點(diǎn):- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應(yīng)商設(shè)備封裝:516-PBGAPGE(27x27) 包裝:托盤
IDT79RC32H435-350BC 功能描述:IC MPU 32BIT CORE 350MHZ 256-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:Interprise™ 標(biāo)準(zhǔn)包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點(diǎn):- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應(yīng)商設(shè)備封裝:516-PBGAPGE(27x27) 包裝:托盤
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