參數(shù)資料
型號: IDT79RC32H435-300BC
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 10/53頁
文件大小: 0K
描述: IC MPU 32BIT CORE 300MHZ 256-BGA
標準包裝: 90
系列: Interprise™
處理器類型: MIPS32 32-位
速度: 300MHz
電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA
供應商設(shè)備封裝: 256-CABGA(17x17)
包裝: 托盤
其它名稱: 79RC32H435-300BC
18 of 53
January 19, 2006
IDT 79RC32435
Figure 4 COLD Reset Operation with External Boot Configuration Vector AC Timing Waveform
Note: For a diagram showing the COLD Reset Operation with Internal Boot Configuration Vector, see Figure 3.6 in the RC32435 User
Reference Manual.
1
1.
EXTBCV is asserted (i.e., pulled-up). COLDRSTN is asserted by external logic. The RC32435 responds by immediately tri-stating the bottom
16-bits of the memory and peripheral address bus (MADDR[15:0]), driving the remaining address bus signals (i.e., MADDR[21:16]), and
asserting RSTN. EXTCLK is undefined at this point.
2.
External logic drives the boot configuration vector on MADDR[15:0].
3.
External logic negates COLDRSTN and tri-states the boot configuration vector on MADDR[15:0]. In response, the RC32435 stops sampling
the boot configuration vector and retains the boot configuration vector value seen two clock cycles earlier (i.e., the value on the MADDR[15:0]
lines two rising edges of CLK earlier). Within 16 CLK clock cycles after COLDRSTN is sampled negated, the RC32435 begins driving
MADDR[15:0].
4.
The RC32435 waits for the NVRAM to initialize (if the Disable NVRAM Initialization mode is not selected in the boot configuration vector) and
for the PLL to stabilize.
5.
The RC32435 then begins generating EXTCLK.
6.
After at least 4000 CLK clock cycles, the RC32435 tri-states RSTN.
7.
At least 4000 CLK clock cycles after negating RSTN, the RC32435 samples RSTN. If RSTN is negated, cold reset has completed and the
RC32435 CPU begins executing by taking MIPS reset exception.
CLK
COLDRSTN
RSTN
MADDR[15:0]
MADDR[21:16]
2
EXTCLK
3
4
5
6
EXTBCV
4000 CLK
clock cycles
Boot Configuration Vector
Driven
*
* COLDRSTN sampled negated(high) by the RC32435
4000 CLK
clock cycles
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