- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4082 > IDT79RC32H434-400BC (IDT, Integrated Device Technology Inc)IC MPU 32BIT CORE 400MHZ 256-BGA PDF資料下載
參數(shù)資料
| 型號： | IDT79RC32H434-400BC |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 34/53頁 |
| 文件大小： | 0K |
| 描述： | IC MPU 32BIT CORE 400MHZ 256-BGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | Interprise™ |
| 處理器類型： | MIPS32 32-位 |
| 速度： | 400MHz |
| 電壓： | 1.2V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-CABGA（17x17） |
| 包裝： | 托盤 |
| 其它名稱： | 79RC32H434-400BC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當(dāng)前第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁
4 of 53
January 19, 2006
IDT RC32434
P
PP
Pin Description Table
in Description Table
The following table lists the functions of the pins provided on the RC32434. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero
(low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Signal
Type
Name/Description
Memory and Peripheral Bus
BDIRN
O
External Buffer Direction. Controls the direction of the external data bus buffer
for the memory and peripheral bus. If the RC32434 memory and peripheral bus
is connected to the A side of a transceiver, such as an IDT74FCT245, then this
pin may be directly connected to the direction control (e.g., BDIR) pin of the
transceiver.
BOEN
O
External Buffer Enable. This signal provides an output enable control for an
external buffer on the memory and peripheral data bus.
WEN
O
Write Enables. This signal is the memory and peripheral bus write enable sig-
nal.
CSN[3:0]
O
Chip Selects. These signals are used to select an external device on the mem-
ory and peripheral bus.
MADDR[21:0]
O
Address Bus. 22-bit memory and peripheral bus address bus.
MADDR[25:22] are available as GPIO alternate functions.
MDATA[7:0]
I/O
Data Bus. 8-bit memory and peripheral data bus. During a cold reset, these pins
function as inputs that are used to load the boot configuration vector.
OEN
O
Output Enable. This signal is asserted when data should be driven by an exter-
nal device on the memory and peripheral bus.
RWN
O
Read Write. This signal indicates whether the transaction on the memory and
peripheral bus is a read transaction or a write transaction. A high level indicates
a read from an external device. A low level indicates a write to an external
device.
WAITACKN
I
Wait or Transfer Acknowledge. When configured as wait, this signal is
asserted during a memory and peripheral bus transaction to extend the bus
cycle. When configured as a transfer acknowledge, this signal is asserted during
a transaction to signal the completion of the transaction.
DDR Bus
DDRADDR[13:0]
O
DDR Address Bus. 14-bit multiplexed DDR address bus. This bus is used to
transfer the addresses to the DDR devices.
DDRBA[1:0]
O
DDR Bank Address. These signals are used to transfer the bank address to the
DDRs.
DDRCASN
O
DDR Column Address Strobe. This signal is asserted during DDR transac-
tions.
DDRCKE
O
DDR Clock Enable. The DDR clock enable signal is asserted during normal
DDR operation. This signal is negated following a cold reset or during a power
down operation.
DDRCKN
O
DDR Negative DDR clock. This signal is the negative clock of the differential
DDR clock pair.
Table 1 Pin Description (Part 1 of 6)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT71V67903S75BG | IC SRAM 9MBIT 75NS 119BGA |
| IDT79RC32H435-350BCI | IC MPU 32BIT CORE 350MHZ 256-BGA |
| IDT79RC32H435-350BCGI | IC MPU 32BIT CORE 350MHZ 256-BGA |
| IDT71V67803S150BG | IC SRAM 9MBIT 150MHZ 119BGA |
| IDT79RC32H434-350BCI | IC MPU 32BIT CORE 350MHZ 256-BGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT79RC32H434-400BCG | 功能描述:IC MPU 32BIT CORE 400MHZ 256-BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:Interprise™ 標(biāo)準(zhǔn)包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點:- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應(yīng)商設(shè)備封裝:516-PBGAPGE（27x27） 包裝:托盤 |
| IDT79RC32H435-266BC | 功能描述:IC MPU 32BIT CORE 266MHZ 256-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:Interprise™ 標(biāo)準(zhǔn)包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點:- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應(yīng)商設(shè)備封裝:516-PBGAPGE（27x27） 包裝:托盤 |
| IDT79RC32H435-266BCG | 功能描述:IC MPU 32BIT CORE 266MHZ 256-BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:Interprise™ 標(biāo)準(zhǔn)包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點:- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應(yīng)商設(shè)備封裝:516-PBGAPGE（27x27） 包裝:托盤 |
| IDT79RC32H435-266BCGI | 功能描述:IC MPU 32BIT CORE 266MHZ 256-BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:Interprise™ 標(biāo)準(zhǔn)包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點:- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應(yīng)商設(shè)備封裝:516-PBGAPGE（27x27） 包裝:托盤 |
| IDT79RC32H435-266BCI | 功能描述:IC MPU 32BIT CORE 266MHZ 256-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:Interprise™ 標(biāo)準(zhǔn)包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點:- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應(yīng)商設(shè)備封裝:516-PBGAPGE（27x27） 包裝:托盤 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。