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參數(shù)資料
| 型號： | IDT74LVCH574AQ |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| 封裝： | QSOP-20 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 63K |
| 代理商： | IDT74LVCH574AQ |
INDUSTRIALTEMPERATURERANGE
IDT74LVCH574A
3.3VCMOSOCTALEDGE-TRIGGEREDD-TYPEFLIP-FLOP
1
AUGUST 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4935/1
FEATURES:
0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
CMOS power levels (0.4
W typ. static)
Rail-to-rail output swing for increased noise margin
All inputs, outputs, and I/O are 5V tolerant
Supports hot insertion
Available in SOIC, SSOP, QSOP, and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
DRIVE FEATURES:
High Output Drivers: ±24mA
Reduced system switching noise
IDT74LVCH574A
DESCRIPTION:
The LVCH574A octal edge-triggered D-type flip-flop is built using ad-
vanced dual-metal CMOS technology. The device features 3-state outputs
designed specifically for driving highly capacitive or relatively low-imped-
ance loads. The LVCH574A is particularly suitable for implementing buffer
registers, input-output (I/O) ports, bidirectional bus drivers, and working
registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to
the logic levels at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs
in either a normal logic state (high or low logic levels) or a high-impedance
state. In the high- impedance state, the outputs neither load nor drive the bus
lines significantly. OEdoes not affect the internal operations of the flip-flops.
Old data can be retained or new data can be entered while the outputs are
in the high-impedance state.
The LVCH574A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining speed
performance.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V system environment.
The LVCH574A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
3.3V CMOS OCTAL EDGE-
TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS, 5 VOLT
TOLERANT I/O AND BUS-HOLD
OE
C1
CLK
1
D
TO SEVEN OTHER CHANNELS
1
11
2
19
1
D
1
Q
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