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參數(shù)資料
| 型號(hào)： | IDT74LVCH244ASO |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 總線收發(fā)器 |
| 英文描述： | LVC/LCX/Z SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| 封裝： | SOIC-20 |
| 文件頁(yè)數(shù)： | 1/6頁(yè) |
| 文件大小： | 64K |
| 代理商： | IDT74LVCH244ASO |
INDUSTRIALTEMPERATURERANGE
IDT74LVCH244A
3.3VCMOSOCTALBUFFER/DRIVERWITH3-STATEOUTPUTS
1
AUGUST 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4625/1
FEATURES:
0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
CMOS power levels (0.4
W typ. static)
Rail-to-rail output swing for increased noise margin
All inputs, outputs, and I/O are 5V tolerant
Supports hot insertion
Available in SOIC, SSOP, QSOP, and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
5V and 3.3V mixed voltage systems
Data communication and telecommunication systems
DRIVE FEATURES:
High Output Drivers: ±24mA
Reduced system switching noise
IDT74LVCH244A
3.3V CMOS
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
AND BUS-HOLD
DESCRIPTION:
The LVCH244A octal buffer/driver is built using advanced dual metal
CMOS technology. This device is organized as two 4-bit line drivers with
separate output-enable (OE) inputs. When OE is low, the device passes
data from the A inputs to the Y outputs. When OE is high, the outputs are
in the high-impedance state.
The LVCH244A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
To ensure the high-impedance state during power up or power down,
OE should be tied to VCC through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
theuseofthisdeviceasatranslatorinamixed3.3V/5Vsystemenvironment.
The LVCH244A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
1
A1
1
A2
1
A3
1
A4
1
Y1
1
Y2
1
Y3
1
Y4
2
A1
2
A2
2
A3
2
A4
2
Y1
2
OE
2
Y2
2
Y3
2
Y4
19
11
9
15
5
7
13
3
17
1
2
4
6
8
18
16
14
12
1
OE
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