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參數(shù)資料
| 型號： | IDT74LVCH2573APG8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| 封裝： | TSSOP-20 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 62K |
| 代理商： | IDT74LVCH2573APG8 |
INDUSTRIALTEMPERATURERANGE
IDT74LVCH2573A
3.3VCMOSOCTALTRANSPARENTD-TYPELATCH
1
FEBRUARY 2000
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2000 Integrated Device Technology, Inc.
DSC-4942/1
FEATURES:
0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
CMOS power levels (0.4
W typ. static)
Rail-to-rail output swing for increased noise margin
All inputs, outputs, and I/O are 5V tolerant
Supports hot insertion
Available in SOIC, SSOP, QSOP, and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
5V and 3.3V mixed voltage systems
Data communication and telecommunication systems
DRIVE FEATURES:
Balanced Output Drivers: ±12mA
Low switching noise
IDT74LVCH2573A
DESCRIPTION:
The LVCH2573A octal transparent D-type latch is built using advanced
dualmetalCMOStechnology.Thedevicefeatures3-stateoutputsdesigned
specifically for driving highly capacitive or relatively low-impedance loads,
and is particularly suitable for implementing buffer registers, input-output (I/
O) ports, bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q outputs follow the data (D)
inputs. When LE is taken low, the Q outputs are latched at the logic levels
at the D inputs.
Abufferedoutput-enable(OE)inputcanbeusedtoplacetheeightoutputs
in either a normal logic state (high or low logic levels) or a high-impedance
state. In the high-impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and increased drive provide
the capability to drive bus lines without interface or pullup components. OE
does not affect the internal operations of the latch. Old data can be retained
ornewdatacanbeenteredwhiletheoutputsareinthehigh-impedancestate.
The LVCH2573A has series resistors in the device output structure which
will significantly reduce line noise when used with light loads. This driver has
been developed to drive ±12mA at the designated thresholds.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
theuseofthisdeviceasatranslatorinamixed3.3V/5Vsystemenvironment.
The LVCH2573A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
3.3V CMOS OCTAL
TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS, 5 VOLT
TOLERANT I/O AND BUS-HOLD
OE
C1
LE
1
D
TO SEVEN OTHER CHANNELS
1
11
2
19
1
D
1
Q
相關PDF資料 |
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| IDT74LVCH2573APY | LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| IDT74LVCH2573AQ | LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| IDT74LVCH2574AQ8 | LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| IDT74LVCH2574APY8 | LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| IDT74LVCH2574APG | LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
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