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參數(shù)資料
| 型號： | IDT74LVCH16652APA8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVC/LCX/Z SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 0.50 MM PITCH, TSSOP-56 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 100K |
| 代理商： | IDT74LVCH16652APA8 |
INDUSTRIALTEMPERATURERANGE
IDT74LVCH16652A
3.3V CMOS 16-BIT BUS TRANSCEIVER AND REGISTER
1
MARCH 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4689/2
FEATURES:
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
CMOS power levels (0.4
W typ. static)
All inputs, outputs, and I/O are 5V tolerant
Supports hot insertion
Available in SSOP, TSSOP, and TVSOP packages
FUNCTIONAL BLOCK DIAGRAM
DRIVE FEATURES:
High Output Drivers: ±24mA
Reduced system switching noise
APPLICATIONS:
5V and 3.3V mixed voltage systems
Data communication and telecommunication systems
IDT74LVCH16652A
DESCRIPTION:
This 16-bit transceiver and register is built using advanced dual metal
CMOS technology. This high-speed, low power device is organized as two
independent 8-bit bus transceivers with 3-state D-type registers. The
control circuitry is organized for multiplexed transmission of data between
A bus and B bus either directly or from the internal storage registers. Each
8-bit transceiver/register features complementary Output Enable (OEAB
and OEBA) inputs to control the transciever functions and Select lines (SAB
andSBA)toselecteitherreal-timedataorstoreddata.Separateclockinputs
are provided for A and B port registers. Data on the A or B data bus, or both,
can be stored in the internal registers by the low-to-high transitions at the
appropriate clock pins. Flow-through organization of signal pins simplifies
layout. All inputs are designed with hysteresis for improved noise margin.
The LVCH16652A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The LVCH16652A has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
3.3V CMOS 16-BIT BUS
TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O, BUS-HOLD
2
B1
1D
C1
1D
C1
2
A1
2
SAB
2
C LKAB
2
SBA
2
O EBA
2
CLKBA
29
30
31
27
26
15
42
2
OEAB
28
A R EG
B RE G
TO SEVEN O THER C HANN ELS
1
B1
1D
C1
1D
C1
1
A1
1
SAB
1
CLKAB
1
SBA
1
OEBA
1
C LKBA
56
55
54
2
3
5
52
1
OEAB
1
A R EG
B R EG
TO SEVEN OTH ER CH AN NELS
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