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參數(shù)資料
| 型號： | IDT74LVC74APG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 鎖存器 |
| 英文描述： | LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 |
| 封裝： | TSSOP-14 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 75K |
| 代理商： | IDT74LVC74APG |
INDUSTRIALTEMPERATURERANGE
IDT74LVC74A
3.3VCMOSDUALPOSITIVE-EDGE-TRIGGEREDD-TYPEFLIP-FLOP
1
OCTOBER 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4626/4
FEATURES:
0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
CMOS power levels (0.4
μμμμμ W typ. static)
Rail-to-Rail output swing for increased noise margin
All inputs, outputs, and I/Os are 5V tolerant
Supports hot insertion
Available in TSSOP package
FUNCTIONAL BLOCK DIAGRAM
DRIVE FEATURES:
High Output Drivers: ±24mA
Reduced system switching noise
APPLICATIONS:
5V and 3.3V mixed voltage systems
Data communication and telecommunication systems
IDT74LVC74A
DESCRIPTION:
This dual positive-edge-triggered D-type flip-flop is built using advanced
dual metal CMOS technology. A low level at the preset (
PRE) or clear (CLR)
inputs sets or resets the outputs, regardless of the levels of the other inputs.
When
PREandCLRareinactive,dataatthedata(D)inputmeetingthesetup
timerequirementsistransferredtotheoutputsonthepositive-goingedgeofthe
clockpulse.Clocktriggeringoccursatavoltagelevelandisnotdirectlyrelated
to the rise time of the clock pulse. Following the hold-time interval, data at the
D input can be changed without affecting the levels at the outputs.
The LVC74A has been designed with a ±24mA output driver. This driver
is capable of driving a moderate to heavy load while maintaining speed
performance.
Inputs can be driven from either 3.3V or 5V devices. This feature allows the
use of this device as a translator in a mixed 3.3V/5V system environment.
TG
C
PRE
CLK
C
TG
C
D
TG
C
TG
C
CLR
Q
4
3
2
1
5
1
6
1
3.3V CMOS DUAL
POSITIVE-EDGE-TRIGGERED D-TYPE
FLIP-FLOP WITH CLEAR AND
PRESET, 5 VOLT TOLERANT I/O
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| IDT74LVC841APY8 | LVC/LCX/Z SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24 |
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| IDT74LVC843AQ8 | LVC/LCX/Z SERIES, 9-BIT DRIVER, TRUE OUTPUT, PDSO24 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT74LVC827APY | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74LVC827ASO | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74LVC861AEPG | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74LVC863AESO | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74LVCC3245APGG | 功能描述:IC BUS TRANSCVR 3-ST 8B 24TSSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 變換器 系列:74LVCC 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:100 系列:- 邏輯功能:變換器，雙向 位數(shù):2 輸入類型:CMOS 輸出類型:CMOS 數(shù)據(jù)速率:16Mbps 通道數(shù):2 輸出/通道數(shù)目:1 差分 - 輸入:輸出:無/無 傳輸延遲（最大）:15ns 電源電壓:1.65 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:10-UFQFN 供應(yīng)商設(shè)備封裝:10-UTQFN（1.4x1.8） 包裝:管件 |
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