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參數(shù)資料
| 型號： | IDT74LVC841APY8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVC/LCX/Z SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24 |
| 封裝： | 0.65 MM PITCH, SSOP-24 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 108K |
| 代理商： | IDT74LVC841APY8 |
1
EXTENDEDCOMMERCIALTEMPERATURERANGE
IDT74LVC841A
3.3V CMOS 10-BIT BUS-INTERFACE D-TYPE LATCH
APRIL 1999
1999
Integrated Device Technology, Inc.
DSC-4695/-
c
IDT74LVC841A
ADVANCE
INFORMATION
EXTENDED COMMERCIAL TEMPERATURE RANGE
DESCRIPTION:
The LVC841A 10-bit bus-interface D-type latch is built using advanced
dual metal CMOS technology. The LVC841A is designed specifically for
FEATURES:
–
0.5 MICRON CMOS Technology
–
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
–
1.27mm pitch SOIC, 0.65mm pitch SSOP,
0.635mm pitch QSOP, 0.65mm pitch TSSOP packages
–
Extended commercial range of – 40°C to +85°C
–VCC = 3.3V ±0.3V, Normal Range
–VCC = 2.3V to 3.6V, Extended Range
–
CMOS power levels (0.4 W typ. static)
–
Rail-to-Rail output swing for increased noise margin
–
All inputs, outputs and I/O are 5 Volt tolerant
–
Supports hot insertion
3.3V CMOS 10-BIT
BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
AND 5 VOLT TOLERANT I/O
Functional Block Diagram
OE
C1
LE
1
D
TO NINE OTHER CHANNELS
1
13
2
23
1
D
1
Q
driving highly capacitive or relatively low-impedance loads. It is particularly
suitable for implementing buffer registers, I/O ports, bidirectional bus drivers,
and working registers.
The ten latches are transparent D-type latches. The device has noninverting
data (D) inputs and provides true data at its outputs.
A buffered output-enable (
OE ) input can be used to place the ten outputs
in either a normal logic state (high or low logic levels) or a high-impedance
state. In the high-impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and increased drive provide
the capability to drive bus lines without interface or pullup components.
OE
does not affect internal operations of the latch. Previously stored data can
be retained or new data can be entered while the outputs are in the high-
impedance state.
The LVC841A has been designed with a ±24mA output driver. This driver
is capable of driving a moderate to heavy load while maintaining speed
performance.
To ensure the high-impedance state during power up or power down,
OE
should be tied to VCC through a pullup resistor; the minimum value of the
resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V system environment.
Drive Features for LVC841A:
–
High Output Drivers:
±24mA
–
Reduced system switching noise
APPLICATIONS:
5V and 3.3V mixed voltage systems
Data communication and telecommunication systems
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