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參數(shù)資料
| 型號： | IDT74LVC137APY8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 編、解碼器及復(fù)用、解復(fù)用 |
| 英文描述： | LVC/LCX/Z SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16 |
| 封裝： | SSOP-16 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 84K |
| 代理商： | IDT74LVC137APY8 |
1
EXTENDEDCOMMERCIALTEMPERATURERANGE
IDT74LVC137A
3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
OCTOBER 1999
1999
Integrated Device Technology, Inc.
DSC-4753/1
c
IDT74LVC137A
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS
3-LINE TO 8-LINE
DECODER/DEMULTIPLEXER,
WITH ADDRESS LATCHES
Drive Features for LVC137A:
– High Output Drivers: ±24mA
– Reduced system switching noise
FEATURES:
– 0.5 MICRON CMOS Technology
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 1.27mm pitch SOIC, 0.635mm pitch QSOP,
0.65mm pitch SSOP, 0.65mm pitch TSSOP packages
– Extended commercial range of – 40°C to +85°C
–VCC = 3.3V ±0.3V, Normal Range
–VCC = 2.3V to 3.6V, Extended Range
– CMOS power levels (0.4W typ. static)
– Rail-to-Rail output swing for increased noise margin
– All inputs, outputs and I/O are 5 Volt tolerant
– Supports hot insertion
Y7
8
Y6
9
Y5
10
Y4
11
Y3
12
Y2
13
Y1
14
Y0
15
Data
O utputs
Select
Inputs
A
B
C
G2A
G2B
G1
1
2
3
4
5
6
Latch
Enable
Output
Enables
APPLICATIONS:
5V and 3.3V mixed voltage systems
Data communication and telecommunication systems
NO
T RECOMMENDED
FOR
NEW
DESIGNS
FOR
NEW
DESIGNS
FOR
NEW
DESIGNS
FOR
NEW
DESIGNS
FOR
NEW
DESIGNS
DESCRIPTION:
The LVC137A 3-line to 8-line decoder/demultiplexer is built using
advanced dual metal CMOS technology. The LVC137A is designed for
high-performance memory-decoding or data-routing applications requir-
ing very short propagation delay times. In high-performance memory
systems, this decoder minimizes the effects of system decoding. When
employedwithhigh-speedmemoriesutilizingafastenablecircuit,thedelay
times of this decoder and the enable time of the memory are usually less
than the typical access time of the memory. This means that the effective
system delay introduced by the decoder is negligible.
When the latch enable (G2A) input is low, the LVC137A acts as a
decoder/demultiplexer.WhenG2Atransitionsfromlowtohigh,theaddress
present at the inputs (A, B, and C) is stored in the latches. Further address
changes are ignored, provided G2A remains high. The output-enable (G1
and G2B) inputs control the outputs independently of the select or latch-
enable inputs. All of the outputs are forced high if G1 is low or G2B is high.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVC137A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
FUNCTIONAL BLOCK DIAGRAM
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| IDT74LVC163APY8 | LVC/LCX/Z SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16 |
| IDT74LVC163AQ8 | LVC/LCX/Z SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16 |
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