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參數(shù)資料
| 型號： | IDT74LVC163AQ8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 計(jì)數(shù)器 |
| 英文描述： | LVC/LCX/Z SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16 |
| 封裝： | QSOP-16 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 100K |
| 代理商： | IDT74LVC163AQ8 |
INDUSTRIALTEMPERATURERANGE
IDT74LVC163A
3.3VCMOSPRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER
1
OCTOBER 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4949/1
FEATURES:
0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
CMOS power levels (0.4
W typ. static)
Rail-to-Rail output swing for increased noise margin
All inputs, outputs, and I/Os are 5V tolerant
Supports hot insertion
Available in QSOP, SOIC, SSOP, and TSSOP packages
FUNCTIONAL DIAGRAM
DRIVE FEATURES:
High Output Drivers: ±24mA
Reduced system switching noise
APPLICATIONS:
5V and 3.3V mixed voltage systems
Data communication and telecommunication systems
STATE DIAGRAM
IDT74LVC163A
DESCRIPTION:
The LVC163A is a synchronous presettable binary counter, which
features an internal look-ahead carry and can be used for high-speed
counting. Synchronous operation is provided by having all the flip-flops
clocked simultaniously on the positive-going edge of the clock (CP).
3.3V CMOS PRESETTABLE
SYNCHRONOUS 4-BIT BINARY
COUNTER WITH SYNCHRONOUS
RESET, 5 VOLT TOLERANT I/O
fmax =
tp(max) (CP to TC) + tsu (CEP to CP)
1
PARALLEL LOAD
CIRCUITRY
BINARY COUNTER
34
5
6
14
13
12
11
Q0
Q1
Q2
Q3
D0
D1
D2
D3
PE
CET
CEP
CP
MR
TC
9
10
7
2
1
15
01
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Outputs (Q0 to Q3) may be preset to a high or low level. A low level at the
parallel enable input (PE) disables the counting action and causes the data
atthedatainputs(D0toD3)tobeloadedintothecounteronthepositive-going
edge of the clock (provided that the set-up and hold time requirements for
PE are met). Preset takes place regardless of the levels at count enable
inputs (CEP and CET). A low level at the master reset input (MR) sets all
fouroutputsoftheflip-flops(Q0toQ3)tolowlevelafterthenextpositive-going
transition on the clock (CP) input (provided that the set-up and hold time
requirements for PE are met).
This action occurs regardless of the levels of CP, PE, CET, and CEP
inputs. This synchronous reset feature enables the designer to modify the
maximum count with only one external NAND gate.
The look-ahead carry simplifies serial cascading of the counters. Both
count enable inputs (CEP and CET) must be high to count. The CET input
is fed forward to enable the terminal count output (TC). The TC output thus
enabled will produce a high output pulse of a duration approximately equal
to a high level output of Q0. This pulse can be used to enable the next
cascaded stage. The maximum clock frequency for the cascaded counters
is determined by the CP to TC propagation delay and CEP to CP set-up
time, according to the following formula:
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