參數(shù)資料
型號: IDT74LVC11APG
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 通用總線功能
英文描述: Adjustable Precision Shunt Regulator 3-TO-92 -40 to 85
中文描述: LVC/LCX/Z SERIES, TRIPLE 3-INPUT AND GATE, PDSO14
封裝: TSSOP-14
文件頁數(shù): 4/5頁
文件大?。?/td> 55K
代理商: IDT74LVC11APG
INDUSTRIAL TEMPERATURE RANGE
4
IDT74LVC11A
3.3V CMOS TRIPLE 3-INPUT AND GATE WITH 5V TOLERANT I/O
Open
V
LOAD
GND
V
CC
Pulse
Generator
D.U.T.
500
500
C
L
R
T
V
IN
V
OUT
(1, 2)
LVC QUAD Link
INPUT
V
IH
V
T
0V
V
OH
V
T
V
OL
V
OH
V
T
V
OL
t
PLH1
t
SK
(x)
OUTPUT 1
OUTPUT 2
t
PHL1
t
SK
(x)
t
PLH2
t
PHL2
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
PHL1
LVC QUAD Link
DATA
INPUT
TIMING
INPUT
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
t
REM
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
t
SU
t
H
t
SU
t
H
V
IH
V
T
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
V
T
t
W
SAME PHASE
INPUT TRANSITION
OPPOSITE PHASE
INPUT TRANSITION
0V
V
OH
V
T
0V
V
OL
t
PLH
t
PHL
t
PHL
t
PLH
OUTPUT
V
T
V
IH
V
T
V
IH
V
T
CONTROL
INPUT
t
PLZ
0V
OUTPUT
NORMALLY
LOW
t
PZH
0V
SWITCH
CLOSED
OUTPUT
NORMALLY
HIGH
ENABLE
DISABLE
SWITCH
OPEN
t
PHZ
0V
V
LZ
V
OL
V
OH
V
HZ
V
T
V
T
t
PZL
V
LOAD/2
V
LOAD/2
V
IH
V
T
LVC QUAD Link
LVC QUAD Link
LVC QUAD Link
LVC QUAD Link
TEST CIRCUITS AND WAV EFORMS
TEST CONDITIONS
Propagation Delay
Test Circuit for All Outputs
Set-up, Hold, and Release Times
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termnation resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
10MHz; t
F
2ns; t
R
2ns.
2. Pulse Generator for All Pulses: Rate
10MHz; t
F
2.5ns; t
R
2.5ns.
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other Tests
Output Skew - t
SK
(
X
)
Pulse Width
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC(1)
= 2.5V±0.2V
2 x Vcc
Vcc
Vcc
/ 2
150
150
30
V
CC(2)
= 3.3V±0.3V & 2.7V
6
2.7
1.5
300
300
50
Unit
V
V
V
mV
mV
pF
Switch
V
LOAD
GND
Open
NOTE:
1. Diagramshown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
相關(guān)PDF資料
PDF描述
IDT74LVC11APY Adjustable Precision Shunt Regulator 3-TO-92 -40 to 85
IDT74LVC11APGG 3.3V CMOS TRIPLE 3-INPUT AND GATE WITH 5 VOLT TOLERANT I/O
IDT74LVC125APG 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O
IDT74LVC125A Adjustable Precision Shunt Regulator 3-TO-92 -40 to 85
IDT74LVC125APY Adjustable Precision Shunt Regulator 3-TO-92 -40 to 85
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