- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67714 > IDT74FCT88915TT133PY8 (INTEGRATED DEVICE TECHNOLOGY INC) FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28 PDF資料下載
參數(shù)資料
| 型號： | IDT74FCT88915TT133PY8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | SSOP-28 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 108K |
| 代理商： | IDT74FCT88915TT133PY8 |
6
COMMERCIALTEMPERATURERANGE
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
GENERAL AC SPECIFICATION NOTES, CONTINUED
8. The wiring diagrams and written explanations of Figures 4a-4c demonstrate the input and output frequency relationships for various possible feedback configurations. The allowable
SYNC input range to stay in the phase-locked condition is also indicated. There are two allowable SYNC frequency ranges, depending on whether FREQ_SEL is HIGH or LOW.
Also, it is possible to feed back the
Q5 output, thus creating a 180° phase shift between the SYNC input and the Q outputs. The table below summarizes the allowable SYNC
frequency range for each possible configuration:
9. The tPD spec describes how the phase offset between the SYNC input and the output connected to the FEEDBACK input varies with process, temperature, and voltage. The phase
measurements were made at 1.5V. The Q/2 output was terminated at the FEEDBACK input with 100
Ω to VCC and 100Ω to ground. tPD measurements were made with the loop
filter connection shown in Figure 2 below:
Figure 2. Loop Filter Connection
External Loop
Filter
0.1F
C1
LF
Analog G N D
Phase Relationship
FREQ_SEL
Feedback
Allowable SYNC Input
Corresponding 2Q Output
of the Q Outputs
Level
Output
Frequency Range (MHz)
Frequency Range
to Rising SYNC Edge
HIGH
Q/2
10 to (2Q fMAX Spec)/4
40 to (2Q fMAX Spec)
0°
HIGH
Any Q (Q0-Q4)
20 to (2Q fMAX Spec)/2
40 to (2Q fMAX Spec)
0°
HIGH
Q5
20 to (2Q fMAX Spec)/2
40 to (2Q fMAX Spec)
180°
HIGH
2Q
40 to (2Q fMAX Spec)
0°
LOW
Q/2
5 to (2Q fMAX Spec)/8
20 to (2Q fMAX Spec)/2
0°
LOW
Any Q (Q0-Q4)
10 to (2Q fMAX Spec)/4
20 to (2Q fMAX Spec)/2
0°
LOW
Q5
10 to (2Q fMAX Spec)/4
20 to (2Q fMAX Spec)/2
180°
LOW
2Q
20 to (2Q fMAX Spec)/2
0°
相關PDF資料 |
PDF描述 |
|---|---|
| IDT74FCT88915TT70PY8 | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28 |
| IDT74SSTU32864GBF | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| IDT74SSTU32864CBF8 | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| IDT74SSTU32864GBFG | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| IDT74SSTU32864ABFG8 | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT74FCT88915TT70PY | 功能描述:IC PLL CLK GENERATOR 28-SSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:74FCT 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| IDT74FST163211PV | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74FST163233PV | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74FST16323PA | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74FST163244DPF | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Integrated Device Technology Inc 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。