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參數(shù)資料
| 型號(hào)： | IDT74FCT841CEB |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES |
| 中文描述： | 高性能CMOS總線接口鎖存 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 140K |
| 代理商： | IDT74FCT841CEB |
7.22
2
IDT54/74FCT841A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
GND
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
Y
9
LE
V
CC
P24-1
D24-1
E24-1
&
SO24-2
DIP/CERPACK/SOIC
TOP VIEW
INDEX
D
2
D
3
D
4
NC
D
5
D
6
D
7
Y
2
Y
3
Y
4
NC
Y
5
Y
6
Y
7
O
D
1
N
V
C
Y
0
D
8
G
L
Y
9
Y
8
LCC
TOP VIEW
L28-1
D
0
Y
1
D
9
N
3
2
20
19
1
4
5
6
7
8
18
17
16
15
14
9
10
11
12 13
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
10
13
14
15
16
17
18
19
20
11
12
21
22
23
24
2607 drw 02
2607 drw 03
PIN DESCRIPTION
FUNCTION TABLE
(1)
Name
CLR
I/O
I
Description
When
CLR
is LOW, the outputs are
LOW if
OE
is LOW. When
CLR
is HIGH,
data can be entered into the latch.
The latch data inputs.
The latch enable input. The latches are
transparent when LE is HIGH. Input
data is latched on the HIGH-to-LOW
transition.
The 3-state latch outputs.
The output enable control. When
OE
is
LOW, the outputs are enabled. When
OE
is HIGH, the outputs (Y
I
) are in the
high-impedance (off) state.
Preset line. When
PRE
is LOW, the
outputs are HIGH if
OE
is LOW. Preset
overrides
CLR
.
D
I
LE
I
I
Y
I
OE
O
I
PRE
I
2607 tbl 01
Inputs
OE
Inter-
nal
Q
I
X
L
Out-
puts
Y
I
Z
Z
CLR PRE
LE
X
H
D
I
X
L
Function
High Z
High Z
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
H
X
L
H
Z
Z
L
High Z
Latched (High Z)
Transparent
NC
L
H
H
H
L
H
H
L
H
L
L
L
L
H
L
X
X
H
X
X
X
H
H
Transparent
Latched
Preset
Clear
NC
H
L
NC
H
L
L
L
H
L
H
L
L
H
H
X
L
L
X
X
X
H
L
H
H
Z
Z
Preset
Latched (High Z)
Latched (High Z)
NOTE:
1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change,
Z = High Impedance
2607 tbl 02
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