參數(shù)資料
型號: IDT74FST3257
廠商: Integrated Device Technology, Inc.
英文描述: QUAD 2:1 MUX/DEMUX BUS SWITCH
中文描述: 四2:1復用/解復用器總線開關(guān)
文件頁數(shù): 1/5頁
文件大小: 93K
代理商: IDT74FST3257
Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGES
AUGUST 1996
1996 Integrated Device Technology, Inc.
10.3
DSC-3257/3
1
QUAD 2:1 MUX/DEMUX
BUS SWITCH
IDT74FST3257
PRELIMINARY
PIN DESCRIPTION
Pin Names
I
0A-
I
0D
I
1A-
I
1D
E
capability. Thus they generate little or no noise of their own
while providing a low resistance path for an external driver.
These devices connect input and output ports through an n-
channel FET. When the gate-to-source junction of this FET is
adequately forward-biased the device conducts or the resis-
tance between input and output ports is small. Without
adequate bias on the gate-to-source junction of the FET, the
FET is turned off, therefore with no V
CC
applied, the device
has hot insertion capability.
The low on-resistance and simplicity of the connection
between input and output ports reduces the delay in this path
to close to zero.
The FST3257 provides a 4-bit 2:1 multiplexer/demultiplexer.
The S pin controls the mux select and the
E
pin serves as the
switch enable.
3257 tbl 01
FEATURES:
Bus switches provide zero delay paths
Extended commercial range of –40
°
C to +85
°
C
Low switch on-resistance:
FST3xxx – 5
TTL-compatible input and output levels
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
Available in QSOP and SOIC
I/O
I/O
I/O
I
Description
Port 0
Port 1
Switch Enable (Active Low)
S
I
Mux Select
Port Z
Z
A-
Z
B
I/O
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
3257 drw 01
3257 drw 02
SOIC/QSOP
TOP VIEW
5
6
7
8
1
2
3
4
14
13
12
11
10
9
I
0A
I
1A
Z
A
S
I
0B
I
1B
Z
B
GND
I
0C
I
1C
Z
C
1
0D
I
1D
Z
D
Vcc
SO16-1
SO16-7
15
16
E
I
0A
Z
A
I
1A
Z
B-D
3 Channels
I
0B-D
I
1B-D
S
E
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
DESCRIPTION:
The FST3257 belongs to IDT's family of Bus switches. Bus
switch devices perform the function of connecting or isolating
two ports without providing any inherent current sink or source
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