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參數(shù)資料
型號: IDT74FCT16952CTPAG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 2/7頁
文件大?。?/td> 0K
描述: IC REGSTERD TRSCVR 16BIT 56TSSOP
標(biāo)準(zhǔn)包裝: 2,000
系列: 74FCT
邏輯類型: 寄存收發(fā)器,非反相
元件數(shù): 2
每個元件的位元數(shù): 8
輸出電流高,低: 32mA,64mA
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 56-TSSOP
包裝: 帶卷 (TR)
其它名稱: 74FCT16952CTPAG8
2
INDUSTRIALTEMPERATURERANGE
IDT74FCT16925AT/CT/ET
FASTCMOS16-BITREGISTEREDTRANSCEIVER
PIN CONFIGURATION
Symbol
Description
Max
Unit
VTERM(2)
Terminal Voltage with Respect to GND
–0.5 to +7
V
VTERM(3)
Terminal Voltage with Respect to GND
–0.5 to VCC+0.5
V
TSTG
Storage Temperature
–65 to +150
° C
IOUT
DC Output Current
–60 to +120
mA
ABSOLUTE MAXIMUM RATINGS(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Output and I/O terminals for FCT162XXX.
Symbol
Parameter(1)
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
3.5
6
pF
COUT
Output Capacitance
VOUT = 0V
3.5
8
pF
CAPACITANCE (TA = +25°C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
SSOP/ TSSOP
TOP VIEW
1
B1
1
B2
GND
1
B3
1
B4
VCC
1
B5
1
B6
1
OEBA
1
B7
1
B8
2
B1
2
B2
GND
2
B3
2
B4
VCC
2
B5
GND
1
CLKBA
2
B7
2
B6
2
B8
GND
2
CLKBA
2
OEBA
1
CLKAB
GND
1
A1
1
A2
VCC
1
A3
1
A4
GND
1
A5
1
A6
1
A7
1
A8
GND
2
A1
2
A2
VCC
2
A3
2
A5
2
A4
2
A7
GND
2
A8
2
CLKAB
2
A6
1
OEAB
1
CEAB
2
OEAB
2
CEAB
2
CEBA
1
CEBA
47
37
38
39
40
41
42
43
44
45
46
33
34
35
36
56
55
49
50
51
52
53
54
48
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
11
21
22
23
24
29
30
31
32
25
26
27
28
FUNCTION TABLE(1,3)
Inputs
Outputs
x
CEAB
xCLKAB
x
OEAB
xAx
xBx
HX
L
X
B
(2)
XL
L
X
B
(2)
L
LL
L
LH
H
XX
H
X
Z
NOTES:
1. A-to-B data flow is shown: B-to-A data flow is similar but uses x
CEBA, xCLKBA, and
x
OEBA.
2. Level of B before the indicated steady-state input conditions were established.
3. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
↑ = LOW-to-HIGH Transition
Z = High-impedance
PIN DESCRIPTION
Pin Names
Description
x
OEAB
A-to-B Output Enable Input (Active LOW)
x
OEBA
B-to-A Output Enable Input (Active LOW)
x
CEAB
A-to-B Clock Enable Input (Active LOW)
x
CEBA
B-to-A Clock Enable Input (Active LOW)
xCLKAB
A-to-B Clock Input
xCLKBA
B-to-A Clock Input
x A x
A-to-B Data Inputs or B-to-A 3-State Outputs
x B x
B-to-A Data Inputs or A-to-B 3-State Outputs
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