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參數(shù)資料
| 型號(hào)： | IDT74ALVCHG162282DF8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ALVC/VCX/A SERIES, 18-BIT EXCHANGER, TRUE OUTPUT, PDSO80 |
| 封裝： | TVSOP-80 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 78K |
| 代理商： | IDT74ALVCHG162282DF8 |
1
IDT74ALVCHG162282
3.3V CMOS 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
COMMERCIALTEMPERATURERANGE
CLK
SEL
1
B1
C1
1D
CE
1D
C1
CE
1D
C1
A1
2
B1
1 of 18 Channels
39
40
25
24
27
OE
42
0
1
C1
1D
DIR
41
CE
1D
C1
CE
1D
C1
NO
T RECOMMENDED
FOR
NEW
DESIGNS
FOR
NEW
DESIGNS
FOR
NEW
DESIGNS
FOR
NEW
DESIGNS
FOR
NEW
DESIGNS
JULY 2000
1999
Integrated Device Technology, Inc.
DSC-4558/-
c
IDT74ALVCHG162282
COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT TO
36-BIT REGISTERED BUS
EXCHANGER WITH 3-STATE
OUTPUTS AND BUS-HOLD
DESCRIPTION:
This 18-bit to 36-bit registered bus exchanger is manufactured using
advanceddualmetalCMOStechnology.TheALVCHG162282isintended
foruseinapplicationsinwhichdatamustbetransferredfromanarrowhigh-
speed bus to a wide lower-frequency bus.
APPLICATIONS:
SDRAM Modules
PC Motherboards
Workstations
The ALVCHG162282 provides synchronous data exchange between
the two ports. Data is stored in the internal registers on the low-to-high
transition of the clock (CLK) input. For data transfer in the B-to-A direction,
the select (SEL) input selects 1B or 2B data for the A outputs. For data
transfer in the A-to-B direction, a two-stage pipeline is provided in the 1B
path, with a single storage register in the 2B path. Data flow is controlled by
the active-low output enable (OE) and the direction-control (DIR) input. The
DIR control pin is registered to synchronize the bus direction changes with
the clock.
A port outputs have equivalent 50
series resistors. B port outputs have
equivalent 20
series resistors.
The switching characteristics in this spec, are based on 25pF (A Port)
and 80pF (B Port) loads, but production test is accomplished with the
standard 50pF load.
The ALVCHG162282 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
– 0.5 MICRON CMOS Technology
–Typical tSK(0) (Output Skew) < 250ps
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 0.40mm pitch TVSOP package
– Commercial range of 0°C to +70°C
–VCC = 3.3V ± 0.3V, Normal Range
– CMOS power levels (0.4W typ. static)
– Rail-to-Rail output swing for increased noise margin
– Low switching noise
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT74ALVCHR16260PF8 | ALVC/VCX/A SERIES, 12 MULTIPLEXER AND DEMUX/DECODER, PDSO56 |
| IDT74ALVCHR16260PA | ALVC/VCX/A SERIES, 12 MULTIPLEXER AND DEMUX/DECODER, PDSO56 |
| IDT74ALVCHR16409PF | ALVC/VCX/A SERIES, 18-BIT EXCHANGER, TRUE OUTPUT, PDSO56 |
| IDT74ALVCHR16409PF8 | ALVC/VCX/A SERIES, 18-BIT EXCHANGER, TRUE OUTPUT, PDSO56 |
| IDT74ALVCHR16501PV | ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
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參數(shù)描述 |
|---|---|
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| IDT74ALVCHR162245PA/TR | 制造商:Integrated Device Technology Inc 功能描述: |
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| IDT74ALVCHR162245PAG8 | 功能描述:IC TRANSCVR TRI-ST 16BIT 48TSSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器 系列:74ALVCHR 標(biāo)準(zhǔn)包裝:1 系列:74LVCR 邏輯類型:收發(fā)器，非反相 元件數(shù):1 每個(gè)元件的位元數(shù):8 輸出電流高，低:12mA，12mA 電源電壓:1.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:20-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:20-VQFN-EP（3.5x4.5） 包裝:剪切帶 (CT) 產(chǎn)品目錄頁面:997 (CN2011-ZH PDF) 其它名稱:296-13981-1 |
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