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參數(shù)資料
| 型號： | IDT74ALVCHR16260PF8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 編、解碼器及復用、解復用 |
| 英文描述： | ALVC/VCX/A SERIES, 12 MULTIPLEXER AND DEMUX/DECODER, PDSO56 |
| 封裝： | TVSOP-56 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 75K |
| 代理商： | IDT74ALVCHR16260PF8 |
1
EXTENDEDCOMMERCIALTEMPERATURERANGE
IDT74ALVCHR16260
3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
JULY 1999
1999 Integrated Device Technology, Inc.
DSC-5167/1
c
IDT74ALVCHR16260
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 12-BIT TO 24-BIT
MULTIPLEXED D-TYPE
LATCH WITH 3-STATE
OUTPUTS AND BUS-HOLD
FEATURES:
– 0.5 MICRON CMOS Technology
–Typical tSK(0) (Output Skew) < 250ps
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 0.635mm pitch SSOP, 0.50mm pitch TSSOP,
and 0.40mm pitch TVSOP packages
– Extended commercial range of – 40°C to + 85°C
–VCC = 3.3V ± 0.3V, Normal Range
–VCC = 2.7V to 3.6V, Extended Range
–VCC = 2.5V ± 0.2V
– CMOS power levels (0.4W typ. static)
– Rail-to-Rail output swing for increased noise margin
APPLICATIONS:
3.3V High Speed Systems
3.3V and lower voltage computing systems
LE1B
LEA1B
OE1B
SEL
OEA
A1:12
LE2B
LEA2B
OE2B
A-1B
LATCH
1B-A
LATCH
A-2B
LATCH
2B-A
LATCH
M
U
X
1
0
12
1
B1:12
2
B1:12
12
30
29
2
28
1
27
55
56
Drive Features for ALVCHR16260:
– Balanced Output Drivers: ±12mA
– Low switching noise
NO
T RECOMMENDED
FOR
NEW
DESIGNS
FOR
NEW
DESIGNS
FOR
NEW
DESIGNS
FOR
NEW
DESIGNS
FOR
NEW
DESIGNS
Functional Block Diagram
DESCRIPTION:
This 12-bit to 24-bit multiplexed D-type latch is built using ad-
vanced dual metal technology. The ALVCHR16260 is used in
applications in which two separate data paths must be multiplexed
onto, or demultiplexed from, a single data path. Typical applications
include multiplexing and/or demultiplexing address and data infor-
mation in microprocessor or bus-interface applications. This device
also is useful in memory interleaving applications.
Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are
available for address and/or data transfer. The output-enable (OE1B,
OE2B, and OEA) inputs control the bus transceiver functions. The
OE1B and OE2B control signals also allow bank control in the A-
to-B direction. Address and/or data information can be stored using
the internal storage latches. The latch-enable (LE1B, LE2B, LEA1B,
and LEA2B) inputs are used to control data storage. When the latch-
enable input is high, the latch is transparent. When the latch-enable
input goes low, the data present at the inputs is latched and remains
latched until the latch-enable input is returned high.
The ALVCHR16260 has series resistors in the device output
structure which will significantly reduce line noise when used with light
loads. This driver has been designed to drive ±12mA at the desig-
nated threshold levels.
The ALVCHR16260 has “bus-hold” which retains the inputs’ last
state whenever the input goes to a high impedance. This prevents
floating inputs and eliminates the need for pull-up/down resistors.
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