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參數(shù)資料
| 型號： | IDT74ALVCH16903 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER, DUAL 3-STATE OUTPUTS AND BUS-HOLD |
| 中文描述： | 3.3V的CMOS 12位通用總線驅(qū)動器，帶有奇偶校驗器，雙程三態(tài)輸出和總線狀態(tài)保持 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 123K |
| 代理商： | IDT74ALVCH16903 |
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
1
J ANUARY 2004
INDUS T RIAL T E MPE RAT URE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2004 Integrated Device Technology, Inc.
DSC-4911/2
FEATURES:
0.5 MICRON CMOS Technology
Typical t
SK(o)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
V
CC
= 3.3V ± 0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
V
CC
= 2.5V ± 0.2V
CMOS power levels (0.4
μ
W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in SSOP and TSSOP packages
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
DRIV E FEATURES:
High Output Drivers: ±24mA
Suitable for heavy loads
IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL
BUS DRIVER WITH PARITY
CHECKER, DUAL 3-STATE
OUTPUTS AND BUS-HOLD
DESCRIPTION:
This 12-bit universal bus driver is built using advanced dual metal CMOS
technology. This device has dual outputs and can operate as a buffer or an
edge-triggered register. In both modes, parity is checked on APAR, which
arrives one cycle after the data to which it applies. The
YERR
output, which is
produced one cycle after APAR, is open drain.
MODE selects one of the two data paths. When MODE is low, the device
operates as an edge-triggered register. On the positive transition of the clock
(CLK) input and when the clock-enable (
CLKEN
) input is low, data setup at the
A inputs is stored in the internal registers. On the positive transition of CLK and
when
CLKEN
is high, only data setup at the 9A-12A inputs is stored in their
internal registers. When MODE is high, the device operates as a buffer and data
at the A inputs passes directly to the outputs. The 11A/
YERREN
serves a dual
purpose; it acts as a normal data bit and also enables
YERR
data to be clocked
into the
YERR
output register.
When used as a single device, parity output enable (
PAROE
) must be tied
high; when parity input/output (PARI/O) is low, even parity is selected and when
PARI/O is high, odd parity is selected. When used in pairs and
PAROE
is low,
the parity sumis output on PARI/O for cascading to the second ALVCH16903.
When used in pairs and
PAROE
is high, PARI/O accepts a partial parity sum
fromthe first ALVCH16903.
A buffered output-enable (
OE
) input can be used to place the 24 outputs and
YERR
in either a normal logic state (high or low logic levels) or a high-impedance
state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the
capability to drive bus lines without need for interface or pullup components.
The ALVCH16903 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining speed
performance.
The ALVCH16903 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high-impedance. This prevents floating inputs
and elimnates the need for pull-up/down resistors.
Symbol
V
TERM
(2)
V
TERM
(3)
Description
Max
Unit
V
V
Termnal Voltage with Respect to GND
Termnal Voltage with Respect to GND
(Outputs Only)
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
I
> V
CC
Continuous Clamp Current, V
O
< 0
Continuous Current through each
V
CC
or GND
–0.5 to +4.6
–0.5 to V
CC
+0.5
T
STG
I
OUT
I
IK
–65 to +150
–50 to +50
±50
°C
mA
mA
I
OK
I
CC
I
SS
–50
±100
mA
mA
ABSOLUTE MAX IMUM RATINGS
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUMRATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximumrating
conditions for extended periods may affect reliability.
2. V
CC
termnals.
3. This value is limted to 4.6V maximum
NOTE:
1. As applicable to the device type.
Symbol
C
IN
C
OUT
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
I/O Port Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
5
7
7
Max.
7
9
9
Unit
pF
pF
pF
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
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