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參數(shù)資料
| 型號： | IDT74AUC16373PFI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 1.8V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS |
| 中文描述： | AUC SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48 |
| 封裝： | TVSOP-48 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 99K |
| 代理商： | IDT74AUC16373PFI |
INDUSTRIAL TEMPERATURE RANGE
IDT74AUC16373
1.8V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
1
FEBRUARY 2003
IDT74AUC16373
INDUS T RIAL T E MPE RAT URE RANGE
1.8V CMOS 16-BIT TRANSPARENT
D-TYPE LATCH WITH
3-STATE OUTPUTS
DESCRIPTION:
This 16-bit transparent D-type latch is built using advanced CMOS technol-
ogy. The device can be used as a single 16-bit latch or as two 8-bit latches. When
the latch enable (LE) input is high, the Q outputs follow the data (D) inputs. When
LE is taken low, the Q outputs are latched at the levels set up at the D inputs.
A buffered output enable (
OE
) input can be used to place the eight outputs
in either a normal logic state (high or low logic levels) or a high-impedance state.
In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The
OE
input does not affect the internal operation of the latch.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the outputs, preventing damaging current backflow
through the device when it is powered down.
To ensure the high-impedance state during power up or power down,
OE
should be tied to V
DD
through a pull-up resistor; the mnimumvalue of the resistor
is determned by the current-sinking capability of the driver.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2003 Integrated Device Technology, Inc.
DSC-6169/9
FEATURES:
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
1.8V Optimized
0.8V to 2.7V Operating Range
Inputs/outputs tolerant up to 3.6V
Output drivers: ±9mA @ 2.3V
Supports hot insertion
Available in TSSOP, TVSOP, and VFBGA packages
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
high performance, low voltage communications systems
high performance, low voltage computing systems
1
Q
1
1
LE
1
D
1
1
OE
1
D
C
1
TO SEVEN OTHER CHANNELS
2
Q
1
2
LE
2
D
1
2
OE
TO SEVEN OTHER CHANNELS
1
D
C
1
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