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參數(shù)資料
| 型號： | IDT74ALVCH162601PA |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 0.50 MM PITCH, TSSOP-56 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 76K |
| 代理商： | IDT74ALVCH162601PA |
INDUSTRIALTEMPERATURERANGE
IDT74ALVCH162601
3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVERWITH3-STATEOUTPUTS
1
MARCH 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4733/1
FEATURES:
0.5 MICRON CMOS Technology
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
VCC = 2.5V ± 0.2V
CMOS power levels (0.4
W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in SSOP, TSSOP, and TVSOP packages
FUNCTIONAL BLOCK DIAGRAM
IDT74ALVCH162601
3.3V CMOS 18-BIT UNIVERSAL
BUS TRANSCEIVER WITH
3-STATE OUTPUTS
AND BUS-HOLD
DESCRIPTION:
This 18-bit universal bus transceiver is built using advanced dual metal
CMOS technology. The ALVCH162601 combines D-type latchesand D-type
flip-flops to allow data flow in transparent, latched, clocked, and clock-enabled
modes.
Dataflowineachdirectioniscontrolledbyoutput-enable(
OEABandOEBA),
latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The
clockcanbecontrolledbytheclock-enable(
CLKENABandCLKENBA)inputs.
For A-to-B data flow, the device operates in the transparent mode when LEAB
is high. When LEAB is low, the A data is latched if CLKAB is held at a high or
low logic level. If LEAB is low, the data is stored in the latch/flip-flop on the low-
to-high transition of CLKAB. When
OEABislow,theoutputsareactive.When
OEAB is high, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA,LEBA,CLKBA
and
CLKENBA.
The ALVCH162601 has series resistors in the device output structure of the
“B”portwhichwillsignificantlyreducelinenoisewhenusedwithlightloads.This
driver has been designed to drive ±12mA at the designated threshold levels.
The “A” port has a ±24mA driver.
The ALVCH162601 has “bus-hold” which retains the inputs’ last state
whenevertheinputgoestoahighimpedance. Thispreventsfloatinginputsand
eliminates the need for pull-up/down resistors.
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
DRIVE FEATURES:
High Output Drivers: ±24mA (A port)
Balanced Output Drivers: ±12mA (B port)
B1
A1
LEA B
CLK BA
OEB A
LEB A
CLK AB
TO 17 OTH ER CH ANN ELS
CE
1D
C1
CE
1D
C1
CLK
CLK EN AB
OEA B
CLK EN BA
27
29
30
2
28
55
56
1
3
54
CLK
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