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參數(shù)資料
| 型號： | IDT74ALVCH162500PV |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 0.635 MM PITCH, SSOP-56 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 113K |
| 代理商： | IDT74ALVCH162500PV |
1
EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74ALVCH162500
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER W/3-STATE OUTPUTS
MARCH 1999
1999 Integrated Device Technology, Inc.
DSC-4533/-
c
IDT74ALVCH162500
ADVANCE
INFORMATION
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT UNIVER-
SAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
AND BUS-HOLD
FEATURES:
–
0.5 MICRON CMOS Technology
–Typical tSK(0) (Output Skew) < 250ps
–
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
–
0.635mm pitch SSOP, 0.50mm pitch TSSOP,
and 0.40mm pitch TVSOP packages
–
Extended commercial range of – 40°C to + 85°C
–VCC = 3.3V ± 0.3V, Normal Range
–VCC = 2.7V to 3.6V, Extended Range
–VCC = 2.5V ± 0.2V
–
CMOS power levels (0.4 W typ. static)
–
Rail-to-Rail output swing for increased noise margin
APPLICATIONS:
3.3V High Speed Systems
3.3V and lower voltage computing systems
Functional Block Diagram
DESCRIPTION:
B1
A1
OEBA
CLKBA
LEBA
CLKAB
OEAB
TO 17 OTHER CHANNELS
C1
1D
CLK
3
27
30
28
2
55
1
54
LEAB
C1
1D
CLK
Drive Features for ALVCH162500:
–
Balanced Output Drivers: ±12mA
–
Low switching noise
This 18-bit universal bus transceiver is built using advanced dual
metal CMOS technology. Data flow in each direction is controlled by
output-enable (OEAB and OEBA), latch enable (LEAB and LEBA) and
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device
operates in transparent mode when LEAB is high. When LEAB is LOW,
the A data is latched if CLKAB is held at a high or low logic level. If LEAB
is LOW, the A bus data is stored in the latch/flip-flop on the high-to-low
transition of CLKAB. OEAB performs the output enable function on the B
port. Data flow from B port to A port is similiar but requires using OEBA,
LEBA and CLKBA. Flow-through organization of signal pins simplifies
layout. All inputs are designed with hysteresis for improved noise
margin.
The ALVCH162500 has series resistors in the device output structure
which will significantly reduce reduce line noise when used with light
loads. This driver has been designed to drive ±12mA at the designated
threshold levels.
The ALVCH162500 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
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