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參數(shù)資料
| 型號(hào)： | IDT74ALVC162525PA |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | TSSOP-56 |
| 文件頁(yè)數(shù)： | 1/7頁(yè) |
| 文件大?。?/td> | 83K |
| 代理商： | IDT74ALVC162525PA |
INDUSTRIALTEMPERATURERANGE
IDT74ALVC162525
3.3VCMOS18-BITREGISTEREDBUSTRANSCEIVERWITH3-STATEOUTPUTS
1
MARCH 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4220/1
FEATURES:
0.5 MICRON CMOS Technology
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
VCC = 2.5V ± 0.2V
CMOS power levels (0.4
W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in SSOP, TSSOP, and TVSOP packages
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
DRIVE FEATURES:
High Output Drivers: ±24mA (A port)
Balanced Output Drivers: ±12mA (B port)
IDT74ALVC162525
3.3V CMOS 18-BIT REGIS-
TERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
AND BUS-HOLD
B1
CE
C1
1D
1
0
CE
C1
1D
CE
C1
1D
CE
C1
1D
CE
C1
1D
OEBA
54
A1
SEL
OEAB
CLKE NAB
CLKE NBA
CLK 2BA
CLK 1BA
CL
KAB
55
30
29
28
1
2
27
56
1 of 18 Channels
3
To 17 O ther Channels
DESCRIPTION:
This 18-bit registered bus transceiver is built using advanced dual metal
CMOS technology. Data flow in each direction is controlled by output-enable
(
OEAB andOEBA)andclock-enable(CLKENABandCLKENBA)inputs.For
the A-to-B data flow, the data flows through a single register. The B-to-A data
canflowthroughafour-stagepipelineregisterpath,orthroughasingleregister
path,dependingonthestateoftheselect(
SEL)input.Dataisstoredintheinternal
registersonthelow-to-hightransitionoftheclock(CLK)input,providedthatthe
appropriate
CLKEN inputs are low. The A-to-B data transfer is synchronized
to the CLKAB input, and B-to-A data transfer is synchronized with the CLK1BA
and CLK2BA inputs.
The ALVCH162525 has series resistors in the device output structure of the
“B”portwhichwillsignificantlyreducelinenoisewhenusedwithlightloads.This
driver has been designed to drive ±12mA at the designated threshold levels.
The “A” port has a ±24mA driver.
To ensure the high-impedance state during power up or power down,
OE
shouldbetiedtoVCCthroughapullupresistor;theminimumvalueoftheresistor
is determined by the current-sinking capability of the driver.
The ALVCH162525 has “bus-hold” which retains the inputs’ last state
whenevertheinputbusgoestoahighimpedance.Thispreventsfloatinginputs
and eliminates the need for pull-up/down resistors.
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