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參數(shù)資料
| 型號： | IDT74ALVC16260PV |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 編、解碼器及復用、解復用 |
| 英文描述： | ALVC/VCX/A SERIES, 12 MULTIPLEXER AND DEMUX/DECODER, PDSO56 |
| 封裝： | 0.635 MM PITCH, SSOP-56 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 70K |
| 代理商： | IDT74ALVC16260PV |
INDUSTRIALTEMPERATURERANGE
IDT74ALVC16260
3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
1
MARCH 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4536/2
FEATURES:
0.5 MICRON CMOS Technology
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
VCC = 2.5V ± 0.2V
CMOS power levels (0.4
W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in SSOP, TSSOP, and TVSOP packages
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
DRIVE FEATURES:
High Output Drivers: ±24mA
Suitable for heavy loads
DESCRIPTION:
This 12-bit to 24-bit multiplexed D-type latch is built using advanced dual
metal CMOS technology. The ALVC16260 is used in applications in which
two separate data paths must be multiplexed onto, or demultiplexed from,
asingledatapath.Typicalapplicationsincludemultiplexingand/ordemultiplexing
address and data information in microprocessor or bus-interface applica-
tions. This device also is useful in memory interleaving applications.
Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are avail-
able for address and/or data transfer. The output-enable (OE2B, OE2B,
and OEA)inputscontrolthebustransceiverfunctions.TheOE2BandOE2B
control signals also allow bank control in the A-to-B direction. Address and/
or data information can be stored using the internal storage latches. The
latch-enable (LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control
data storage. When the latch-enable input is high, the latch is transparent.
When the latch-enable input goes low, the data present at the inputs is
latched and remains latched until the latch-enable input is returned high.
The ALVC16260 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
IDT74ALVC16260
3.3V CMOS 12-BIT TO
24-BIT MULTIPLEXED
D-TYPE LATCH WITH
3-STATE OUTPUTS
LE1B
LEA1B
OE1B
SEL
OEA
A1:12
LE2B
LEA2B
OE2B
A-1B
LATCH
1B-A
LATC H
A-2B
LATCH
2B-A
LATCH
M
U
X
1
0
12
1
B1:12
2
B1:12
12
30
29
2
28
1
27
55
56
相關PDF資料 |
PDF描述 |
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| IDT74ALVC16260PA8 | ALVC/VCX/A SERIES, 12 MULTIPLEXER AND DEMUX/DECODER, PDSO56 |
| IDT74ALVC162835APF | ALVC/VCX/A SERIES, 18-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| IDT74ALVC162835APV | ALVC/VCX/A SERIES, 18-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| IDT74ALVC162835APA | ALVC/VCX/A SERIES, 18-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| IDT74ALVC162835PV | ALVC/VCX/A SERIES, 18-BIT DRIVER, TRUE OUTPUT, PDSO56 |
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