- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4583 > IDT72V51446L6BB8 (IDT, Integrated Device Technology Inc)IC FLOW CTRL MULTI QUEUE 256-BGA PDF資料下載
參數(shù)資料
| 型號： | IDT72V51446L6BB8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 56/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FLOW CTRL MULTI QUEUE 256-BGA |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 多隊列流量控制 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BBGA |
| 供應(yīng)商設(shè)備封裝： | 256-BGA（17x17） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 72V51446L6BB8 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁當(dāng)前第56頁第57頁
8
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72V51436/72V51446/72V51456 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
PIN DESCRIPTIONS (CONTINUED)
FSTR
PAFn Flag Bus
LVTTL
addressed via the WRADD bus is selected on the rising edge of WCLK provided that FSTR is HIGH. If
(Continued) Strobe
INPUT
Polled operations has been selected, FSTR should be tied inactive, LOW. Note, that a
PAFn flag bus
selectioncannotbemade,(FSTRmustNOTgoactive)untilprogrammingoftheparthasbeencompleted
and
SENO has gone LOW.
FSYNC
PAFn Bus Sync
LVTTL
FSYNC is an output from the multi-queue device that provides a synchronizing pulse for the
PAFn bus
OUTPUT
duringPolledoperationofthe
PAFnbus.DuringPolledoperationeachsectorofqueuestatusflagsisloaded
on to the
PAFn bus outputs sequentially based on WCLK. The first WCLK rising edge loads sector 1 on
to
PAFn,thesecondWCLKrisingedgeloadssector2.ThethirdWCLKrisingedgewillagainloadsector1.
During the WCLK cycle that sector 1 of a selected device is placed on to the
PAFnbus,theFSYNCoutput
will be HIGH. For sector 2 of that device, the FSYNC output will be LOW.
FXI
PAFn Bus
LVTTL
The FXI input is used when multi-queue devices are connected in expansion mode and Polled
PAFn
Expansion In
INPUT
bus operation has been selected. FXI of device ‘N’ connects directly to FXO of device ‘N-1’. The FXI
receives a token from the previous device in a chain. In single device mode the FXI input must be tied
LOW if the
PAFnbusisoperatedindirectmode.IfthePAFnbusisoperatedinpolledmodetheFXIinput
must be connected to the FXO output of the same device. In expansion mode the FXI of the first device
should be tied LOW, when direct mode is selected.
FXO
PAFn Bus
LVTTL
FXO is an output that is used when multi-queue devices are connected in expansion mode and Polled
Expansion Out
OUTPUT
PAFnbusoperationhasbeenselected.FXOofdevice‘N’connectsdirectlytoFXIofdevice‘N+1’.This
pin pulses when device N has placed its 2nd sector on to the
PAFnbuswithrespecttoWCLK.Thispulse
(token) is then passed on to the next device in the chain ‘N+1’ and on the next WCLK rising edge the first
sector of device N+1 will be loaded on to the
PAFnbus.ThiscontinuesthroughthechainandFXOofthe
last device is then looped back to FXI of the first device. The FSYNC output of each device in the chain
provides synchronization to the user of this looping event.
ID[2:0](1)
Device ID Pins
LVTTL
For the 16Q multi-queue device the WRADD and RDADD address busses are 8 bits wide. When a queue
INPUT
selection takes place the 3 MSb’s of this 8 bit address bus are used to address the specific device (the
5 LSb’s are used to address the queue within that device). During write/read operations the 3 MSb’s
of the address are compared to the device ID pins. The first device in a chain of multi-queue’s (connected
in expansion mode), may be setup as ‘000’, the second as ‘001’ and so on through to device 8 which
is ‘111’, however the ID does not have to match the device order. In single device mode these pins should
be setup as ‘000’ and the 3 MSb’s of the WRADD and RDADD address busses should be tied LOW. The
ID[2:0] inputs setup a respective devices ID during master reset. These ID pins must not toggle during
any device operation. Note, the device selected as the ‘Master’ does not have to have the ID of ‘000’.
IW(1)
InputWidth
LVTTL
ThispinisusedinconjunctionwithOWandBMtosetuptheinputandoutputbuswidthstobeacombination
INPUT
of x9, x18 or x36, (providing that one port is x36).
MAST(1)
Master Device
LVTTL
The state of this input at Master Reset determines whether a given device (within a chain of devices), is the
INPUT
MasterdeviceoraSlave.IfthispinisHIGH,thedeviceisthemasterifitisLOWthenitisaSlave.Themaster
device is the first to take control of all outputs after a master reset, all slave devices go to High-Impedance,
preventing bus contention. If a multi-queue device is being used in single device mode, this pin must
be set HIGH.
MRS
Master Reset
LVTTL
Amasterresetisperformedbytaking
MRSfromHIGHtoLOW,toHIGH.Deviceprogrammingisrequired
INPUT
aftermasterreset.
OE
OutputEnable
LVTTL
TheOutputenablesignalisanAsynchronoussignalusedtoprovidethree-statecontrolofthemulti-queue
INPUT
data output bus, Qout. If a device has been configured as a “Master” device, the Qout data outputs will
be in a Low Impedance condition if the
OEinputisLOW.IfOE isHIGHthentheQoutdataoutputswillbe
in High Impedance. If a device is configured a “Slave” device, then the Qout data outputs will always be
inHighImpedanceuntilthatdevicehasbeenselectedontheReadPort,atwhichpoint
OEprovidesthree-
state of that respective device.
OV
Output Valid Flag
LVTTL
Thisoutputflagprovidesoutputvalidstatusforthedatawordpresentonthemulti-queueflow-controldevice
OUTPUT
data output port, Qout. This flag is therefore, 2-stage delayed to match the data output path delay. That
is, there is a 2 RCLK cycle delay from the time a given queue is selected for reads, to the time the
OVflag
represents the data in that respective queue. When a selected queue on the read port is read to empty,
Symbol
Name
I/O TYPE
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72V51443L6BB8 | IC FLOW CTRL MULTI QUEUE 256-BGA |
| LT1020CSW#TR | IC REG LDO ADJ 125MA 16SOIC |
| MIC5259-3.3YML TR | IC REG LDO 3.3V .3A 6-MLF |
| LT1020CSW#TRPBF | IC REG LDO ADJ 125MA 16-SOIC |
| LFECP15E-3FN256C | IC FPGA 15.3KLUTS 195I/O 256-BGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72V51446L7-5BB | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51446L7-5BB8 | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51446L7-5BBI | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51453L6BB | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51453L6BB8 | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。