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| 型號： | IDT72V51433L7-5BB |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 17/50頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FLOW CTRL MULTI QUEUE 256-BGA |
| 標準包裝： | 1 |
| 類型： | 多隊列流量控制 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BBGA |
| 供應(yīng)商設(shè)備封裝： | 256-BGA（17x17） |
| 包裝： | 托盤 |
| 其它名稱： | 72V51433L7-5BB |
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24
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51433/72V51443/72V51453 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
PAFn FLAG BUS OPERATION
The IDT72V51433/72V51443/72V51453 multi-queue flow-control devices
can be configured for up to 16 queues, each queue having its own almost full
status.Anactivequeuehasitsflagstatusoutputtothediscreteflags,
FFandPAF,
on the write port. Queues that are not selected for a write operation can have
their
PAFstatusmonitoredviathePAFnbus.ThePAFnflagbusis8bitswide,
so that 8 queues at a time can have their status output to the bus. If 9 or more
queues are setup within a device then there are 2 methods by which the device
can share the bus between queues, "Direct" mode and "Polled" mode
depending on the state of the FM (Flag Mode) input during a Master Reset. If
8orlessqueuesaresetupwithinadevicetheneachwillhaveitsowndedicated
output from the bus. If 8 or less queues are setup in single device mode, it is
recommended to configure the
PAFnbustopolledmodeasitdoesnotrequire
using the write address (WRADD).
PAFn - DIRECT BUS
IfFMisLOWatmasterresetthenthe
PAFnbusoperatesinDirect(addressed)
mode. In direct mode the user can address the sector of queues they require
to be placed on to the
PAFn bus. For example, consider the operation of the
PAFnbuswhen10queueshavebeensetup.Tooutputstatusofthefirstsector,
Queue[0:7] the WRADD bus is used in conjunction with the FSTR (
PAF flag
strobe) input and WCLK. The address present on the significant bit of the
WRADDbuswithFSTRHIGHwillbeselectedasthesectoraddressonarising
edge of WCLK. So to address sector 1, Queue[0:7] the WRADD bus should be
loaded with “xxxxxx0”, the
PAFnbuswillchangestatustoshowthenewsector
selected1WCLKcycleaftersectorselection.
PAFn[0:7]getsstatusofqueues,
Queue[0:7] respectively.
To address the second sector, Queue[8:15], the WRADD address is
“xxxxxx1”.
PAF[0:1]getsstatusofqueues,Queue[9:10]respectively.Remem-
ber,only10queuesweresetup,sowhensector2isselectedtheunusedoutputs
PAF[2:7] will be don't care states.
Note, that if a read or write operation is occurring to a specific queue, say
queue ‘x’ on the same cycle as a sector switch which will include the queue ‘x’,
then there may be an extra WCLK cycle delay before that queues status is
correctly shown on the respective output of the
PAFnbus.However,theactive
PAF flagwillshowcorrectstatusatalltimes.
Sectorscanbeselectedonconsecutiveclockcycles,thatisthesectoronthe
PAFnbuscanchangeeveryWCLKcycle.Also,datapresentontheinputbus,
Din, can be written into a queue on the same WCLK rising edge that a sector
isbeingselected,theonlyrestrictionbeingthatawritequeueselectionand
PAFn
sector selection cannot be made on the same cycle.
If 8 or less queues are setup then queues, Queue[0:7] have their
PAFstatus
output on
PAF[0:7]constantly.
Whenthemulti-queuedevicesareconnectedinexpansionofmorethanone
devicethe
PAFnbussesofalldevicesareconnectedtogether,whenswitching
between sectors of different devices the user must utilize the 3 most significant
bits of the WRADD address bus (as well as the 2 LSB’s). These 3 MSB’s
correspond to the device ID inputs, which are the static inputs, ID0, ID1 & ID2.
Please refer to Figure 23
PAFn - Direct Mode Sector Selection for timing
information. Also refer to Table 1, Write Address Bus, WRADD.
PAFn – POLLED BUS
If FM is HIGH at master reset then the
PAFnbusoperatesinPolled(looped)
mode. In polled mode the
PAFnbusautomaticallycyclesthroughthe2sectors
within the device regardless of how many queues have been setup in the part.
EveryrisingedgeoftheWCLKcausesthenextsectortobeloadedonthe
PAFn
bus. The device configured as the master (MAST input tied HIGH), will take
control of the
PAFn after MRS goesLOW.ForthewholeWCLKcyclethatthe
first sector is on
PAFntheFSYNC(PAFnbussync)outputwillbeHIGH,forthe
2nd sector, this FSYNC output will be LOW. This FSYNC output provides the
user with a mark with which they can synchronize to the
PAFnbus,FSYNCis
always HIGH for the WCLK cycle that the first sector of a device is present on
the
PAFn bus.
When devices are connected in expansion mode, only one device will be
set as the Master, MAST input tied HIGH, all other devices will have MAST tied
LOW. The master device is the first device to take control of the
PAFnbusand
will place its first sector on the bus on the rising edge of WCLK after the
MRS
input goes HIGH. For the next 3 WCLK cycles the master device will maintain
control of the
PAFn bus and cycle its sectors through it, all other devices hold
their
PAFnoutputsinHigh-Impedance.Whenthemasterdevicehascycledits
sectorsitpassesatokentothenextdeviceinthechainandthatdeviceassumes
control of the
PAFn bus and then cycles its sectors and so on, the PAFn bus
controltokenbeingpassedonfromdevicetodevice.Thistokenpassingisdone
via the FXO outputs and FXI inputs of the devices (“
PAF Expansion Out” and
“
PAFExpansionIn”).TheFXOoutputofthemasterdeviceconnectstotheFXI
oftheseconddeviceinthechainandtheFXOofthesecondconnectstotheFXI
of the third and so on. The final device in a chain has its FXO connected to the
FXI of the first device, so that once the
PAFnbushascycledthroughallsectors
of all devices, control of the
PAFn will pass to the master device again and so
on. The FSYNC of each respective device will operate independently and
simply indicate when that respective device has taken control of the bus and is
placing its first sector on to the
PAFn bus.
When operating in single device mode the FXI input must be connected to
theFXOoutputofthesamedevice.Insingledevicemodeatokenisstillrequired
to be passed into the device for accessing the
PAFn bus.
Please refer to Figure 26,
PAFn Bus – Polled Mode for timing information.
PAEn FLAG BUS OPERATION
The IDT72V51433/72V51443/72V51453 multi-queue flow-control devices
canbeconfiguredforupto16queues,eachqueuehavingitsownalmostempty
status.Anactivequeuehasitsflagstatusoutputtothediscreteflags,
OVandPAE,
on the read port. Queues that are not selected for a read operation can have
their
PAEstatusmonitoredviathePAEnbus.ThePAEnflagbusis8bitswide,
so that 8 queues at a time can have their status output to the bus. If 9 or more
queues are setup within a device then there are 2 methods by which the device
can share the bus between queues, "Direct" mode and "Polled" mode
depending on the state of the FM (Flag Mode) input during a Master Reset. If
8orlessqueuesaresetupwithinadevicetheneachwillhaveitsowndedicated
output from the bus. If 8 or less queues are setup in single device mode, it is
recommended to configure the
PAFnbustopolledmodeasitdoesnotrequire
using the write address (WRADD).
PAEn - DIRECT BUS
IfFMisLOWatmasterresetthenthe
PAEnbusoperatesinDirect(addressed)
mode. In direct mode the user can address the sector of queues they require
to be placed on to the
PAEn bus. For example, consider the operation of the
PAEnbuswhen10queueshavebeensetup.Tooutputstatusofthefirstsector,
Queue[0:7] the RDADD bus is used in conjunction with the ESTR (
PAE flag
strobe) input and RCLK. The address present on the least significant bit of the
RDADD bus with ESTR HIGH will be selected as the sector address on a rising
edge of RCLK. So to address sector 1, Queue[0:7] the RDADD bus should be
loaded with “xxxxxx0”, the
PAEnbuswillchangestatustoshowthenewsector
selected 1 RCLK cycle after sector selection.
PAEn[0:7]getsstatusofqueues,
Queue[0:7] respectively.
To address the 2nd sector, Queue[8:15], the RDADD address is “xxxxxx1”.
PAE[0:1]getsstatusofqueues,Queue[9:10]respectively.Remember,only10
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| IDT72V51433L7-5BB8 | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51433L7-5BBI | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51436L6BB | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51436L6BB8 | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51436L7-5BB | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
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