參數(shù)資料
型號(hào)： IDT72V51236L7-5BBI
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 45/56頁(yè)
文件大小： 0K
描述： IC FLOW CTRL MULTI QUEUE 256-BGA
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 多隊(duì)列流量控制
安裝類(lèi)型： 表面貼裝
封裝/外殼： 256-BBGA
供應(yīng)商設(shè)備封裝： 256-BGA（17x17）
包裝： 托盤(pán)
其它名稱(chēng)： 72V51236L7-5BBI
5
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
DETAILED DESCRIPTION
MULTI-QUEUE STRUCTURE
The IDT multi-queue flow-control device has a single data input port and
single data output port with up to 4 FIFO queues in parallel buffering between
the two ports. The user can setup between 1 and 4 Queues within the device.
Thesequeuescanbeconfiguredtoutilizethetotalavailablememory,providing
theuserwithfullflexibilityandabilitytoconfigurethequeuestobevariousdepths,
independent of one another.
MEMORY ORGANIZATION/ ALLOCATION
The memory is organized into what is known as “blocks”, each block being
256x36bits.Whentheuserisconfiguringthenumberofqueuesandindividual
queue sizes the user must allocate the memory to respective queues, in units
of blocks, that is, a single queue can be made up from 0 to m blocks, where m
is the total number of blocks available within a device. Also the total size of any
given queue must be in increments of 256 x36. For the IDT72V51236/
72V51246 and IDT72V51256 the Total Available Memory is 64, 128 and 256
blocks respectively (a block being 256 x36). Queues can be built from these
blocks to make any size queue desired and any number of queues desired.
BUS WIDTHS
Theinputportiscommontoallqueueswithinthedevice,asistheoutputport.
ThedeviceprovidestheuserwithBusMatchingoptionssuchthattheinputport
and output port can be either x9, x18 or x36 bits wide provided that at least one
of the ports is x36 bits wide, the read and write port widths being set
independentlyofoneanother.Becausetheportsarecommontoallqueuesthe
width of the queues is not individually set, so that the input width of all queues
are equal and the output width of all queues are equal.
WRITING TO & READING FROM THE MULTI-QUEUE
Data being written into the device via the input port is directed to a discrete
queue via the write queue select address inputs. Conversely, data being read
fromthedevicereadportisreadfromaqueueselectedviathereadqueueselect
addressinputs.Datacanbesimultaneouslywrittenintoandreadfromthesame
queue or different queues. Once a queue is selected for data writes or reads,
the writing and reading operation is performed in the same manner as
conventional IDT synchronous FIFO, utilizing clocks and enables, there is a
single clock and enable per port. When a specific queue is addressed on the
write port, data placed on the data inputs is written to that queue sequentially
basedontherisingedgeofawriteclockprovidedsetupandholdtimesaremet.
Conversely, data is read on to the output port after an access time from a rising
edge on a read clock.
Theoperationofthewriteportiscomparabletothefunctionofaconventional
FIFO operating in standard IDT mode. Write operations can be performed on
thewriteportprovidedthatthequeuecurrentlyselectedisnotfull,afullflagoutput
provides status of the selected queue. The operation of the read port is
comparable to the function of a conventional FIFO operating in FWFT mode.
When a queue is selected on the output port, the next word in that queue will
automaticallyfallthroughtotheoutputregister.Allsubsequentwordsfromthat
queue require an enabled read cycle. Data cannot be read from a selected
queueifthatqueueisempty,thereadportprovidesanOutputValidflagindicating
when data read out is valid. If the user switches to a queue that is empty, the
last word from the previous queue will remain on the output register.
Asmentioned,thewriteporthasafullflag,providingfullstatusoftheselected
queue.Alongwiththefullflagadedicatedalmostfullflagisprovided,thisalmost
full flag is similar to the almost full flag of a conventional IDT FIFO. The device
provides a user programmable almost full flag for all 4 queues and when a
respectivequeueisselectedonthewriteport,thealmostfullflagprovidesstatus
for that queue. Conversely, the read port has an output valid flag, providing
status of the data being read from the queue selected on the read port. As well
as the output valid flag the device provides a dedicated almost empty flag. This
almostemptyflagissimilartothealmostemptyflagofaconventionalIDTFIFO.
The device provides a user programmable almost empty flag for all 4 queues
andwhenarespectivequeueisselectedonthereadport,thealmostemptyflag
provides status for that queue.
PROGRAMMABLE FLAG BUSSES
Inadditiontothesededicatedflags,full&almostfullonthewriteportandoutput
valid&almostemptyonthereadport,therearetwoflagstatusbusses.Analmost
full flag status bus is provided, this bus is 4 bits wide. Also, an almost empty flag
status bus is provided, again this bus is 4 bits wide. The purpose of these flag
busses is to provide the user with a means by which to monitor the data levels
within queues that may not be selected on the write or read port. As mentioned,
the device provides almost full and almost empty registers (programmable by
the user) for each of the 4 queues in the device.
The4bit
PAEnand4bitPAFnbussesprovideadiscretestatusoftheAlmost
Empty and Almost Full conditions of all 4 queue's. If the device is programmed
for less than 4 queue's, then there will be a corresponding number of active
outputs on the
PAEn and PAFn busses.
The flag busses can provide a continuous status of all queues. If devices are
connectedinexpansionmodetheindividualflagbussescanbeleftinadiscrete
form,providingconstantstatusofallqueues,orthebussesofindividualdevices
can be connected together to produce a single bus of 4 bits. The device can
then operate in a "Polled" or "Direct" mode.
When operating in polled mode the flag bus provides status of each device
sequentially,thatis,oneachrisingedgeofaclocktheflagbusisupdatedtoshow
the status of each device in order. The rising edge of the write clock will update
the Almost Full bus and a rising edge on the read clock will update the Almost
Emptybus.
When operating in direct mode the device driving the flag bus is selected by
the user. The user addresses the device that will take control of a respective
flag bus, these
PAFn and PAEn flag busses operating independently of one
another. Addressing of the Almost Full flag bus is done via the write port and
addressing of the Almost Empty flag bus is done via the read port.
PACKET MODE
The multi-queue flow-control device also offers a “Packet Mode” operation.
Packet Mode is user selectable and requires the device to be configured with
both write and read ports as 36 bits wide. In packet mode, users can define
the length of packets or frame by using the two most significant bits of the 36-
bit word. Bit 34 is used to mark the Start of Packet (SOP) and bit 35 is used to
mark the End of Packet (EOP) as shown in Table 5). When writing data into
a given queue, the first word being written is marked, by the user setting bit 34
as the “Start of Packet” (SOP) and the last word written is marked as the “End
of Packet” (EOP) with all words written between the Start of Packet (SOP)
marker (bit 34) and the End of packet (EOP) packet marker (bit 35) constituting
the entire packet. A packet can be any length the user desires, up to the total
available memory in the multi-queue flow-control device. The device monitors
the SOP (bit 34) and looks for the word that contains the EOP (bit 35). The read
port is supplied with an additional status flag, “Packet Ready”. The Packet
Ready (
PR)flaginconjunctionwithOutputValid(OV)indicateswhenatleast
one packet is available to read. When in packet mode the almost empty flag
status, provides packet ready flag status for individual queues.
相關(guān)PDF資料
PDF描述
IDT72V51236L6BB IC FLOW CTRL MULTI QUEUE 256-BGA
IDT72V51246L7-5BB IC FLOW CTRL MULTI QUEUE 256-BGA
MIC5322-PNYMT TR IC REG LDO 3V/2.85V .15A 6MLF
IDT72V51446L7-5BB8 IC FLOW CTRL MULTI QUEUE 256-BGA
LFECP10E-3FN484I IC FPGA 10.2KLUTS 484FPBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT72V51243L6BB 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類(lèi)別:集成電路 (IC) >> 專(zhuān)用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類(lèi)型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類(lèi)型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT72V51243L6BB8 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類(lèi)別:集成電路 (IC) >> 專(zhuān)用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類(lèi)型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類(lèi)型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT72V51243L6BBG 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:是 類(lèi)別:集成電路 (IC) >> 專(zhuān)用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類(lèi)型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類(lèi)型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT72V51243L7-5BB 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類(lèi)別:集成電路 (IC) >> 專(zhuān)用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類(lèi)型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類(lèi)型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT72V51243L7-5BB8 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類(lèi)別:集成電路 (IC) >> 專(zhuān)用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類(lèi)型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類(lèi)型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*