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| 型號： | IDT72V51236L7-5BBI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 2/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FLOW CTRL MULTI QUEUE 256-BGA |
| 標準包裝： | 1 |
| 類型： | 多隊列流量控制 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BBGA |
| 供應(yīng)商設(shè)備封裝： | 256-BGA（17x17） |
| 包裝： | 托盤 |
| 其它名稱： | 72V51236L7-5BBI |
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10
IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PIN DESCRIPTIONS (CONTINUED)
Symbol
Name
I/O TYPE
Description
Q[35:0]
Data Output Bus
LVTTL
These are the 36 data output pins. Data is read out of the device via these output pins on the rising edge
Qout
OUTPUT
of RCLK provided that
REN is LOW, OE is LOW and the queue is selected. Note, that in Packet mode
Q32-Q35maybeusedaspacketmarkers,pleaseseepacketreadyfunctionaldiscussionformoredetail.
Due to bus matching not all outputs may be used, any unused outputs should not be connected.
RADEN
Read Address
LVTTL
The RADEN input is used in conjunction with RCLK and the RDADD address bus to select a queue to
Enable
INPUT
be read from. A queue addressed via the RDADD bus is selected on the rising edge of RCLK provided
that RADEN is HIGH. RADEN should be asserted (HIGH) only during a queue change cycle(s). RADEN
should not be permanently tied HIGH. RADEN cannot be HIGH for the same RCLK cycle as ESTR. Note,
that a read queue selection cannot be made, (RADEN must NOT go active) until programming of the part
has been completed and
SENO has gone LOW.
RCLK
Read Clock
LVTTL
When enabled by
REN, the rising edge of RCLK reads data from the selected queue via the output
INPUT
bus Qout. The queue to be read is selected via the RDADD address bus and a rising edge of RCLK
while RADEN is HIGH. A rising edge of RCLK in conjunction with ESTR and RDADD will also select the
device to be placed on the
PAEn/PRn bus during direct flag operation. During polled flag operation the
PAEn/PRnbusiscycledwithrespecttoRCLKandtheESYNCsignalissynchronizedtoRCLK.ThePAE,
PR and OV outputs are all synchronized to RCLK. During device expansion the EXO and EXI signals
are based on RCLK. RCLK must be continuous and free-running.
RDADD
Read Address Bus
LVTTL
For the 4Q device the RDADD bus is 6 bits. The RDADD bus is a dual purpose address bus. The first
[5:0]
INPUT
functionofRDADDistoselectaqueuetobereadfrom.Theleastsignificant2bitsofthebus,RDADD[1:0]
areusedtoaddress1of4possiblequeueswithinamulti-queuedevice.Addresspin,RDADD[2]provides
the user with a Null-Q address. If the user does not wish to address one of the 4 queues, a Null-Q can
be addressed using this pin. The Null-Q operation is discussed in more detail later. The most significant
3 bits, RDADD[5:3] are used to select 1 of 8 possible multi-queue devices that may be connected in
expansion mode. These 3 MSb’s will address a device with the matching ID code. The address present
on the RDADD bus will be selected on a rising edge of RCLK provided that RADEN is HIGH, (note, that
data can be placed on to the Qout bus, read from the previously selected queue on this RCLK edge). On
the next rising RCLK edge after a read queue select, a data word from the previous queue will be placed
ontotheoutputs,Qout,regardlessofthe
RENinput.TwoRCLKrisingedgesafterreadqueueselect,data
will be placed on to the Qout outputs from the newly selected queue, regardless of
REN due to the first
word fall through effect.
The second function of the RDADD bus is to select the device of queues to be loaded on to the
PAEn/
PRn bus during strobed flag mode. The most significant 3 bits, RDADD[5:3] are again used to select 1
of 8 possible multi-queue devices that may be connected in expansion mode. Address bits RDADD[2:0]
are don’t care during device selection. The device address present on the RDADD bus will be selected
on the rising edge of RCLK provided that ESTR is HIGH, (note, that data can be placed on to the Qout
bus, read from the previously selected Queue on this RCLK edge). Please refer to Table 2 for details
on RDADD bus.
REN
Read Enable
LVTTL
The
RENinputenablesreadoperationsfromaselectedqueuebasedonarisingedgeofRCLK.Aqueue
INPUT
to be read from can be selected via RCLK, RADEN and the RDADD address bus regardless of the state
of
REN.DatafromanewlyselectedqueuewillbeavailableontheQoutoutputbusonthesecondRCLK
cycle after queue selection regardless of
RENduetotheFWFToperation.Areadenableisnotrequired
to cycle the
PAEn/PRn bus (in polled mode) or to select the device , (in direct mode).
SCLK
Serial Clock
LVTTL
If serial programming of the multi-queue device has been selected during master reset, the SCLK input
INPUT
clocks the serial data through the multi-queue device. Data setup on the SI input is loaded into the device
ontherisingedgeofSCLKprovidedthat
SENIisenabled,LOW.Whenexpansionofdevicesisperformed
the SCLK of all devices should be connected to the same source.
SENI
Serial Input Enable
LVTTL
During serial programming of a multi-queue device, data loaded onto the SI input will be clocked into the
INPUT
part (via a rising edge of SCLK), provided the
SENI input of that device is LOW. If multiple devices are
cascaded,the
SENIinputshouldbeconnectedtotheSENOoutputofthepreviousdevice.Sowhenserial
loading of a given device is complete, its
SENO output goes LOW, allowing the next device in the chain
to be programmed (
SENOwillfollowSENIofagivendeviceoncethatdeviceisprogrammed).TheSENI
input of the master device (or single device), should be controlled by the user.
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| IDT72V51243L6BB | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51243L6BB8 | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51243L6BBG | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51243L7-5BB | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51243L7-5BB8 | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
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