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參數(shù)資料
| 型號： | IDT72V3654L10PF8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 4/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BI FIFO 4096X36 10NS 128QFP |
| 標(biāo)準包裝： | 1,000 |
| 系列： | 72V |
| 功能： | 異步 |
| 存儲容量： | 147K（4K x 36） |
| 數(shù)據(jù)速率： | 100MHz |
| 訪問時間： | 10ns |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-TQFP（14x20） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 72V3654L10PF8 |
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12
COMMERCIALTEMPERATURERANGE
IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
Once the Master Reset (
MRS1, MRS2) input is HIGH, a LOW on the BE/
FWFTinputduringthenextLOW-to-HIGHtransitionofCLKA(forFIFO1)and
CLKB (for FIFO2) will select FWFT mode. This mode uses the Output Ready
function (ORA, ORB) to indicate whether or not there is valid data at the data
outputs (A0-A35 or B0-B35). It also uses the Input Ready function (IRA, IRB)
to indicate whether or not the FIFO memory has any free space for writing.
In the FWFT mode, the first word written to an empty FIFO goes directly to data
outputs, no read request necessary. Subsequent words must be accessed
by performing a formal read operation.
Following Master Reset, the level applied to the BE/
FWFTinputtochoose
the desired timing mode must remain static throughoutFIFOoperation.Refer
to Figure 3 (Master Reset) for a First Word Fall Through select timing diagram.
PROGRAMMING THE ALMOST-EMPTY AND ALMOST-FULL FLAGS
Four registers in the IDT72V3654/72V3664/72V3674 are used to hold the
offset values for the Almost-Empty and Almost-Full flags. The Port B Almost-
Empty flag (
AEB) Offset register is labeled X1 and the Port A Almost-Empty
flag (
AEA) Offset register is labeled X2. The Port A Almost-Full flag (AFA)
OffsetregisterislabeledY1andthePortBAlmost-Fullflag(
AFB)Offsetregister
islabeledY2.TheindexofeachregisternamecorrespondstoitsFIFOnumber.
TheoffsetregisterscanbeloadedwithpresetvaluesduringtheresetofaFIFO,
programmed in parallel using the FIFO’s Port A data inputs, or programmed
in serial using the Serial Data (SD) input (see Table 1).
FS0/SD, FS1/
SEN and FS2 function the same way in both IDT Standard
and FWFT modes.
— PRESET VALUES
ToloadaFIFO’sAlmost-EmptyflagandAlmost-FullflagOffsetregisterswith
oneofthefivepresetvalueslistedinTable1,theflagselectinputsmustbeHIGH
or LOW during a master reset. For example, to load the preset value of 64 into
X1andY1,FS0,FS1andFS2mustbeHIGHwhenFlFO1reset(
MRS1)returns
HIGH. Flag-offset registers associated with FIFO2 are loaded with one of the
preset values in the same way with FIFO2 Master Reset (
MRS2), toggled
simultaneously with FIFO1 Master Reset (
MRS1). For relevant preset value
loading timing diagram, see Figure 3.
PARALLEL LOAD FROM PORT A
To program the X1, X2, Y1, and Y2 registers from Port A, perform a Master
Reset on both FlFOs simultaneously with FS2 HIGH or LOW, FS0 and FS1
LOWduringtheLOW-to-HIGHtransitionofMRS1andMRS2.ThestateofFS2
at this point of reset will determine whether the parallel programming method
has Interspersed Parity or Non-Interspersed Parity. Refer to Table 1 for Flag
Programming Flag Offset setup . It is important to note that once parallel
programming has been selected during a Master Reset by holding both FS0
& FS1 LOW, these inputs must remain LOW during all subsequent FIFO
operation. They can only be toggled HIGH when future Master Resets are
performed and other programming methods are desired.
After this reset is complete, the first four writes to FIFO1 do not store data
in RAM but load the Offset registers in the order Y1, X1, Y2, X2. For Non-
InterspersedParitymodethePortAdatainputsusedbytheOffsetregistersare
(A10-A0), (A11-A0), or (A12-A0) for the IDT72V3654, IDT72V3664, or
IDT72V3674,respectively.ForInterspersedParitymodethePortAdatainputs
used by the Offset registers are (A11-A9, A7-A0), (A12-A9, A7-A0), or (A13-
A9, A7-A0) for the IDT72V3654, IDT72V3664, or IDT72V3674, respectively.
The highest numbered input is used as the most significant bit of the binary
number in each case. Valid programming values for the registers range from
1 to 2,044 for the IDT72V3654; 1 to 4,092 for the IDT72V3664; and 1 to 8,188
for the IDT72V3674. After all the offset registers are programmed from Port A,
NOTES:
1. X1 register holds the offset for
AEB; Y1 register holds the offset for AFA.
2. X2 register holds the offset for
AEA; Y2 register holds the offset for AFB.
3. When this method of parallel programming is selected, Port A will assume Non-Interspersed Parity.
4. When IP Mode is selected, only parallel programming of the offset values via Port A, can be performed and Port A will assume Interspersed Parity.
5. IF parallel programming is selected during a Master Reset, then FS0 & FS1 must remain LOW during FIFO operation.
FS2
FS1/
SEN
FS0/SD
MRS1
MRS2
X1 AND Y1 REGlSTERS(1)
X2 AND Y2 REGlSTERS(2)
HH
H
↑
X64
X
HH
H
X
↑
X64
HH
L
↑
X16
X
HH
L
X
↑
X16
HL
H
↑
X8
X
HL
H
X
↑
X8
LH
H
↑
X
256
X
LH
H
X
↑
X
256
LL
H
↑
X
1,024
X
LL
H
X
↑
X
1,024
LH
L
↑↑
Serial programming via SD
HL
L
↑↑
Parallel programming via Port A(3,5)
LL
L
↑↑
IP Mode(4, 5)
TABLE 1 — FLAG PROGRAMMING
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| IDT72V3654L15PF | 功能描述:IC BI FIFO 4096X36 15NS 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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| IDT72V3656L10PF | 功能描述:IC SYNC FIFO 4096X36 10NS 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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| IDT72V3656L10PFI | 制造商:Integrated Device Technology Inc 功能描述:IC SYNC FIFO 4096X36 10NS 128QFP |
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