8
COMMERCIALTEMPERATURERANGE
IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT72V3654/72V3664/72V3674 with CLKA
andCLKBsettofS. Alldatainputsanddataoutputschangestateduringeachclockcycletoconsumethehighestsupplycurrent. Dataoutputsweredisconnected
to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of these device's inputs driven by TTL
HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
PT = VCC x ICC(f) +
Σ(CL x VCC2 x fo)
N
where:
N
=
number of used outputs (36-bit (long word), 18-bit (word) or 9-bit (byte) bus size)
CL
=
output capacitance load
fo
=
switching frequency of an output
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
0
10
20
3040
506070
0
10
20
30
40
50
60
fS
Clock Frequency MHz
ICC(f)
Supply
Current
mA
fdata = 1/2 fS
TA = 25
°C
CL = 0 pF
4664 drw03
70
90
80
100
80
90
100
VCC = 3.3V
VCC = 3.6V
VCC = 3.0V