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參數(shù)資料
| 型號(hào)： | IDT72V3642L10PF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 24/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO SYNC 3.3V CMOS 120-TQFP |
| 標(biāo)準(zhǔn)包裝： | 45 |
| 系列： | 72V |
| 功能： | 同步 |
| 存儲(chǔ)容量： | 72k（1k x 36 x 2） |
| 數(shù)據(jù)速率： | 100MHz |
| 訪問時(shí)間： | 10ns |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 120-LQFP |
| 供應(yīng)商設(shè)備封裝： | 120-TQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | 72V3642L10PF 800-1534 |
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IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
Symbol
Name
I/O
Description
A0-A35
Port A Data
I/0
36-bitbidirectionaldataportforsideA.
AEA
PortAAlmost-
O
Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in FIFO2 is
EmptyFlag
(Port A) less than or equal to the value in the Almost-Empty A Offset register, X2.
AEB
PortBAlmost-
O
ProgrammableAlmost-EmptyflagsynchronizedtoCLKB.ItisLOWwhenthenumberof words in FIFO1 is
EmptyFlag
(Port B) less than or equal to the value in the Almost-Empty B Offset register, X1.
AFA
PortAAlmost-
O
ProgrammableAlmost-FullflagsynchronizedtoCLKA.ItisLOWwhenthenumberofempty locationsin
Full Flag
(Port A) FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1.
AFB
PortBAlmost-
O
ProgrammableAlmost-FullflagsynchronizedtoCLKB.ItisLOWwhenthenumberofempty locationsin
Full Flag
(Port B) FIFO2 is less than or equal to the value in the Almost-Full B Offset register, Y2.
B0 - B35
Port B Data
I/O
36-bitbidirectionaldataportforsideB.
CLKA
Port A Clock
I
CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or
coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all synchronized to the LOW-to-HIGH
transitionofCLKA.
CLKB
Port B Clock
I
CLKB is a continuous clock that synchronizes all data transfers through port Band can be asynchronous or
coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB are synchronized to the LOW-to-HIGH
transitionofCLKB.
CSA
Port A Chip
I
CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write on port A. The A0-A35
Select
outputs are in the high-impedance state when CSA is HIGH.
CSB
Port B Chip
I
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. The
Select
B0- B35 outputs are in the high-impedance state when CSB is HIGH.
EFA/ORA
PortAEmpty/
O
This is a dual function pin. In the IDT Standard mode, the EFA function is selected. EFA indicates
OutputReady
whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA function is selected. ORA
Flag
indicates the presence of valid data on A0-A35 outputs, available for reading. EFA/ORA is synchronized
totheLOW-to-HIGHtransitionofCLKA.
EFB/ORB
PortBEmpty/
O
This is a dual function pin. In the IDT Standard mode, the EFB function is selected. EFB indicates
OutputReady
whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB function is selected. ORB
Flag
indicates the presence of valid data on B0-B35 outputs, available for reading. EFB/ORB is synchronized to
theLOW-to-HIGHtransitionofCLKB.
ENA
Port A Enable
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
ENB
Port B Enable
I
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
FFA/IRA
Port A Full/
O
This is a dual function pin. In the IDT Standard mode, the FFA function is selected. FFA indicates whether
Input Ready
or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA indicates whether or
Flag
not there is space available for writing to the FIFO1 memory. FFA/IRA is synchronized to the LOW-to-
HIGHtransitionofCLKA.
FFB/IRB
Port B Full/
O
This is a dual function pin. In the IDT Standard mode, the FFB function is selected. FFB indicates whether
Input Ready
or not the FIFO2 memory is full. In the FWFT mode, the IRB function is selected. IRB indicates whether or
Flag
not there is space available for writing to the FIFO2 memory. FFB/IRB is synchronized to the LOW-to-
HIGHtransitionofCLKB.
FWFT
FirstWordFall
I
This pin selects the timing mode. A HIGH on FWFT selects IDT Standard mode, a LOW selects First
Through Mode
Word Fall Through mode. Once the timing mode has been selected, the level on FWFT must be static
throughoutdeviceoperation.
FS1, FS0
FlagOffset
I
A LOW-to-HIGH transition of the FIFO Reset input latches the values of FS0 and FS1. If either FS0 or
Selects
FS1 is HIGH when the FIFO Reset input goes HIGH, one of three preset values is selected as the
offset for FIFOs Almost-Full and Almost-Empty flags. If both FIFOs are reset simultaneously and both
FS0 and FS1 are LOW when RST1 and RST2 go HIGH, the first four writes to FIFO1 load the Almost-
Empty and Almost-Full offsets for both FIFOs.
PIN DESCRIPTIONS
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72V3642L10PF8 | 功能描述:IC FIFO 1MX72 10NS 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3642L10PFG | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 3.3V CMOS 120-TQFP |
| IDT72V3642L10PFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 1MX72 10NS 120QFP |
| IDT72V3642L10PQF | 功能描述:IC FIFO 1MX72 10NS 132QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3642L15PF | 功能描述:IC FIFO 1MX72 15NS 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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